From f74ab10060553cd08c0b3e12a351e69f85c225b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Jun 2022 22:38:39 +0100 Subject: [PATCH] mention instruction duplication (which SV does not do) --- svp64-primer/summary.tex | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index a7ecdca59..99e800f98 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -6,6 +6,8 @@ ONLY uses scalar instructions. \item The Power ISA v3.1 Specification is not altered in any way. v3.1 Code-compatibility is guaranteed. \item Does not require sacrificing 32-bit Major Opcodes. +\item Does not require adding duplicates of instructions + (popcnt, popcntw, popcntd, vpopcntb, vpopcnth, vpopcntw, vpopcntd) \item Specifically designed to be easily implemented on top of an existing Micro-architecture (especially Superscalar Out-of-Order Multi-issue) without @@ -33,6 +35,9 @@ size, which as outlined in \cite{SIMD_HARM} has an indirect reduction in power consumption due to less I-Cache/TLB pressure and also Issue remaining idle for long periods. +Simple-V has been specifically and carefully crafted to respect +the Power ISA's Supercomputing pedigree. + \pagebreak \subsection{What is SIMD?} -- 2.30.2