From f755665f4a19929675065830cdb16551b565b84c Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 16 May 2020 14:05:55 -0400 Subject: [PATCH] Implement mtocrf (which isn't different from mtcrf?) --- src/soc/cr/main_stage.py | 9 +++++++++ src/soc/cr/test/test_pipe_caller.py | 10 +++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py index 4a27fcd4..1552c4b1 100644 --- a/src/soc/cr/main_stage.py +++ b/src/soc/cr/main_stage.py @@ -65,6 +65,13 @@ class CRMainStage(PipeModBase): # There's no field, just have to grab it directly from the insn comb += lut.eq(self.i.ctx.op.insn[6:10]) + + # Ugh. mtocrf and mtcrf have one random bit differentiating + # them. This bit is not in any particular field, so this + # extracts that bit from the instruction + move_one = Signal(reset_less=True) + comb += move_one.eq(self.i.ctx.op.insn[20]) + with m.Switch(op.insn_type): with m.Case(InternalOp.OP_MCRF): # MCRF copies the 4 bits of crA to crB (for instance @@ -108,6 +115,7 @@ class CRMainStage(PipeModBase): fxm = Signal(xfx_fields['FXM'][0:-1].shape()) comb += fxm.eq(xfx_fields['FXM'][0:-1]) + # mtcrf mask = Signal(32, reset_less=True) for i in range(8): @@ -115,6 +123,7 @@ class CRMainStage(PipeModBase): comb += cr_output.eq((self.i.a[0:32] & mask) | (self.i.cr & ~mask)) + comb += self.o.cr.eq(cr_output) comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py index 42133771..ccb41a76 100644 --- a/src/soc/cr/test/test_pipe_caller.py +++ b/src/soc/cr/test/test_pipe_caller.py @@ -92,7 +92,15 @@ class CRTestCase(FHDLTestCase): initial_regs[2] = random.randint(0, (1<<32)-1) self.run_tst_program(Program(lst), initial_regs=initial_regs, initial_cr=cr) - + def test_mtocrf(self): + for i in range(20): + mask = 1<