From f7819650979d1fa5339af3eacfa1af1090bf53e8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 3 Nov 2014 15:34:56 -0800 Subject: [PATCH] i965: Disable fast color clears on Skylake for now. We're not programming the clear values yet, so this won't work. This patch should be (effectively) reverted eventually. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_clear.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 0e5fef59e9f..12314204803 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -242,7 +242,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) } /* Clear color buffers with fast clear or at least rep16 writes. */ - if (brw->gen >= 6 && mask & BUFFER_BITS_COLOR) { + if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) { if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) { debug_mask("blorp color", mask & BUFFER_BITS_COLOR); mask &= ~BUFFER_BITS_COLOR; -- 2.30.2