From f79102d67b0e9081badb54e4a84934311a967705 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 10 Nov 2020 15:16:29 +0000
Subject: [PATCH] arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode

Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/miscregs.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 8110a191d..825811fd1 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4907,9 +4907,9 @@ ISA::initializeMiscRegMetadata()
       .hyp().mon()
       .mapsTo(MISCREG_VTCR);
     InitReg(MISCREG_VSTTBR_EL2)
-      .hyp().mon();
+      .hypSecure().mon();
     InitReg(MISCREG_VSTCR_EL2)
-      .hyp().mon();
+      .hypSecure().mon();
     InitReg(MISCREG_TTBR0_EL3)
       .mon();
     InitReg(MISCREG_TCR_EL3)
-- 
2.30.2