From f7a0c32d38db53d628e8d72d2424b44efcfc26c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 2 Jul 2022 17:59:34 +0100 Subject: [PATCH] fix setvl CTR mode --- openpower/isa/simplev.mdwn | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index a933fcd9..3b185c9a 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -32,18 +32,16 @@ Pseudo-code: GPR(_RT) <- [0]*57 || step else VLimm <- SVi + 1 - if vs = 0 then - VL <- SVSTATE[7:13] - else if _RA != 0 then - VL <- (RA)[57:63] - else if _RT != 0 then - VL <- CTR - else - VL <- VLimm[0:6] - if ms = 1 then - MVL <- VLimm[0:6] - else - MVL <- SVSTATE[0:6] + # set or get MVL + if ms = 1 then MVL <- VLimm[0:6] + else MVL <- SVSTATE[0:6] + # set or get VL + if vs = 0 then VL <- SVSTATE[7:13] + else if _RA != 0 then VL <- (RA)[57:63] + else if _RT = 0 then VL <- VLimm[0:6] + else if CTR >u 0b1111111 then VL = 0b1111111 + else VL <- CTR[57:63] + # limit VL to within MVL if VL >u MVL then VL <- MVL SVSTATE[0:6] <- MVL -- 2.30.2