From f7a4d2260460ef60bdf19b26dce8650f8247e93d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Mar 2021 11:12:36 +0000 Subject: [PATCH] add Rc=1 SVP64 unit test to svp64_cases.py --- src/soc/fu/alu/test/svp64_cases.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index 335e3bfd..8761fdc4 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -75,6 +75,30 @@ class SVP64ALUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) + def case_4_sv_add_(self): + # adds: + # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234 + # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111 + isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0xffffffffffffffff + initial_regs[10] = 0x1111 + initial_regs[5] = 0x1 + initial_regs[6] = 0x2223 + + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl[0:7] = 2 # VL + svstate.maxvl[0:7] = 2 # MAXVL + print("SVSTATE", bin(svstate.spr.asint())) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate) + @skip_case("VL hardware loop is not yet implemented") def case_4_sv_check_vl_0(self): # adds: -- 2.30.2