From f7ab4e0cc4e56a7830d407fd708e3ffa408d06d6 Mon Sep 17 00:00:00 2001 From: Topi Pohjolainen Date: Thu, 7 Apr 2016 18:50:56 +0300 Subject: [PATCH] i965/blorp: Prepare stencil sampling for gen8 Signed-off-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 04a019e0717..b567b42e523 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -94,7 +94,8 @@ brw_blorp_surface_info::set(struct brw_context *brw, * program swizzle the coordinates. */ this->map_stencil_as_y_tiled = true; - this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM; + this->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT : + BRW_SURFACEFORMAT_R8_UNORM; break; case MESA_FORMAT_Z24_UNORM_X8_UINT: /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 7cf809b4066..15247594ed7 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -711,9 +711,9 @@ brw_blorp_blit_program::compile(struct brw_context *brw, alloc_regs(); compute_frag_coords(); - /* Render target and texture hardware don't support W tiling. */ + /* Render target and texture hardware don't support W tiling until Gen8. */ const bool rt_tiled_w = false; - const bool tex_tiled_w = false; + const bool tex_tiled_w = brw->gen >= 8 && key->src_tiled_w; /* The address that data will be written to is determined by the * coordinates supplied to the WM thread and the tiling and sample count of -- 2.30.2