From f7b589930d5b4c27adce4b8d703d1a6a71b1151f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 20:33:55 +0100 Subject: [PATCH] move mul data struct to separate module --- src/ieee754/fpmul/datastructs.py | 28 ++++++++++++++++++++++++++++ src/ieee754/fpmul/mul0.py | 20 ++------------------ src/ieee754/fpmul/mul1.py | 2 +- 3 files changed, 31 insertions(+), 19 deletions(-) create mode 100644 src/ieee754/fpmul/datastructs.py diff --git a/src/ieee754/fpmul/datastructs.py b/src/ieee754/fpmul/datastructs.py new file mode 100644 index 00000000..26914e5d --- /dev/null +++ b/src/ieee754/fpmul/datastructs.py @@ -0,0 +1,28 @@ +"""IEEE754 Floating Point Multiplier Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" + +from nmigen import Signal + +from ieee754.fpcommon.fpbase import FPNumBaseRecord +from ieee754.fpcommon.getop import FPPipeContext + + +class FPMulStage0Data: + + def __init__(self, pspec): + width = pspec.width + self.z = FPNumBaseRecord(width, False) + self.out_do_z = Signal(reset_less=True) + self.oz = Signal(width, reset_less=True) + mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1 + self.product = Signal(mw, reset_less=True) + self.ctx = FPPipeContext(pspec) + self.muxid = self.ctx.muxid + + def eq(self, i): + return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), + self.product.eq(i.product), self.ctx.eq(i.ctx)] + diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py index 428c2753..97821a65 100644 --- a/src/ieee754/fpmul/mul0.py +++ b/src/ieee754/fpmul/mul0.py @@ -4,30 +4,14 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton """ -from nmigen import Module, Signal, Cat, Elaboratable +from nmigen import Module, Signal, Cat from nmigen.cli import main, verilog from nmutil.pipemodbase import PipeModBase from ieee754.fpcommon.fpbase import FPNumBaseRecord from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.getop import FPPipeContext - - -class FPMulStage0Data: - - def __init__(self, pspec): - width = pspec.width - self.z = FPNumBaseRecord(width, False) - self.out_do_z = Signal(reset_less=True) - self.oz = Signal(width, reset_less=True) - mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1 - self.product = Signal(mw, reset_less=True) - self.ctx = FPPipeContext(pspec) - self.muxid = self.ctx.muxid - - def eq(self, i): - return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), - self.product.eq(i.product), self.ctx.eq(i.ctx)] +from ieee754.fpmul.datastructs import FPMulStage0Data class FPMulStage0Mod(PipeModBase): diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py index 67e91517..b83432ff 100644 --- a/src/ieee754/fpmul/mul1.py +++ b/src/ieee754/fpmul/mul1.py @@ -4,7 +4,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton """ -from nmigen import Module, Signal, Elaboratable +from nmigen import Module, Signal from nmigen.cli import main, verilog from nmutil.pipemodbase import PipeModBase -- 2.30.2