From f7b82e8cfaf5efcbfbd5e173ee35b0fe416871fe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 10 Jul 2020 11:34:19 +0100 Subject: [PATCH] only pass in lhs bit_width * 2 for UDivRem --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 79f5f9fb..a6a65cc8 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -224,6 +224,10 @@ class DivPipeCoreSetupStage(Elaboratable): self.core_config = core_config self.i = self.ispec() self.o = self.ospec() + if core_config.supported == [DP.UDivRem]: + self.compare_len = bw * 2 + else: + self.compare_len = bw * 3 def ispec(self): """ Get the input spec for this pipeline stage.""" @@ -251,7 +255,7 @@ class DivPipeCoreSetupStage(Elaboratable): comb += self.o.quotient_root.eq(0) comb += self.o.root_times_radicand.eq(0) - lhs = Signal(self.core_config.bit_width * 3, reset_less=True) + lhs = Signal(self.compare_len, reset_less=True) fw = self.core_config.fract_width with m.Switch(self.i.operation): -- 2.30.2