From f7beda5cc8a6e9cb98e500c39e3292516e8a2c7d Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 7 Jan 2021 10:39:53 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 697a5425a..b40aa46e4 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -20,7 +20,7 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]] Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero. Setting bit 22 causes an illegal exception. -Note that in immediate setting mode VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1. 0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero be done via the [[SV SPRs|sv/sprs]] +Note that in immediate setting mode VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1. 0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SV SPRs|sv/sprs]] Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise -- 2.30.2