From f7dd2fb2e2b750f0fb9dedaf885c17bc6beef1f7 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 7 Feb 2019 17:12:23 +0000 Subject: [PATCH] Arm: Backport hlt to all architectures. The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1. --- gas/ChangeLog | 8 +++++ gas/config/tc-arm.c | 13 +++++++- gas/testsuite/gas/arm/armv8a-automatic-hlt.d | 2 ++ gas/testsuite/gas/arm/hlt.d | 35 ++++++++++++++++++++ gas/testsuite/gas/arm/hlt.s | 22 ++++++++++++ opcodes/ChangeLog | 4 +++ opcodes/arm-dis.c | 3 +- 7 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/arm/hlt.d create mode 100644 gas/testsuite/gas/arm/hlt.s diff --git a/gas/ChangeLog b/gas/ChangeLog index cbef618bbca..53f4c68d12c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2019-02-07 Tamar Christina + + * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for + hlt to armv1. + * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs + * testsuite/gas/arm/hlt.d: New test. + * testsuite/gas/arm/hlt.s: New test. + 2019-02-07 Tamar Christina * testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 81b5ceedcc9..e6600f6b10e 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -20187,11 +20187,22 @@ static const struct asm_opcode insns[] = #define THUMB_VARIANT & arm_ext_v8 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), - TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), + +/* Defined in V8 but is in undefined encoding space for earlier + architectures. However earlier architectures are required to treat + this instuction as a semihosting trap as well. Hence while not explicitly + defined as such, it is in fact correct to define the instruction for all + architectures. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v1 +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v1 + TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), + /* ARMv8 T32 only. */ #undef ARM_VARIANT #define ARM_VARIANT NULL diff --git a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d index ee6c428538f..9ce94d36c92 100644 --- a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d +++ b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d @@ -5,4 +5,6 @@ Attribute Section: aeabi File Attributes Tag_CPU_arch: v8 Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-2 + diff --git a/gas/testsuite/gas/arm/hlt.d b/gas/testsuite/gas/arm/hlt.d new file mode 100644 index 00000000000..b05c1fb8d64 --- /dev/null +++ b/gas/testsuite/gas/arm/hlt.d @@ -0,0 +1,35 @@ +#objdump: -d +# This test is only valid on ELF based ports. +#notarget: *-*-pe *-*-wince + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+:\s+ba80 hlt 0x0000 +[^:]+:\s+ba8f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+ba80 hlt 0x0000 +[^:]+:\s+ba8f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+ba80 hlt 0x0000 +[^:]+:\s+ba8f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+ba80 hlt 0x0000 +[^:]+:\s+ba8f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+ba80 hlt 0x0000 +[^:]+:\s+ba8f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f +[^:]+:\s+e1000070 hlt 0x0000 +[^:]+:\s+e100007f hlt 0x000f diff --git a/gas/testsuite/gas/arm/hlt.s b/gas/testsuite/gas/arm/hlt.s new file mode 100644 index 00000000000..02d1316bcac --- /dev/null +++ b/gas/testsuite/gas/arm/hlt.s @@ -0,0 +1,22 @@ +# Test that hlt is available for all architectures. +.macro gen_for_arch arch, has_thumb + .arch \arch + .ifc "yes","\has_thumb" + .thumb + hlt + hlt 0xf + .endif + .arm + hlt + hlt 0xf +.endm + +gen_for_arch armv8-a, yes +gen_for_arch armv7-a, yes +gen_for_arch armv6, yes +gen_for_arch armv5t, yes +gen_for_arch armv4t, yes +gen_for_arch armv3, no +gen_for_arch armv2, no +gen_for_arch armv1, no + diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2523b312a9d..84271305bba 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2019-02-07 Tamar Christina + + * arm-dis.c (arm_opcodes): Redefine hlt to armv1. + 2019-02-07 Tamar Christina PR binutils/23212 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 488522770f8..71d7c524a22 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1788,7 +1788,8 @@ static const struct opcode32 arm_opcodes[] = /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x0320f005, 0x0fffffff, "sevl"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + /* Defined in V8 but is in NOP space so available to all arch. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, -- 2.30.2