From f7de41ef4c6b155fccfbc022c359176154a5ffca Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Oct 2018 13:11:53 +0100 Subject: [PATCH] clarify bitwidth --- simple_v_extension/specification.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index fa8eb6b85..aaf45034c 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1300,8 +1300,9 @@ rd bitwidths). The pseudo-code is therefore as follows: if (int_vec[rs1].isvector)  { irs1 += 1; } if (int_vec[rs2].isvector)  { irs2 += 1; } -Whilst sign-extension and zero-extension implementations are left out -due to each operation being different, the above should be clear that; +Whilst specific sign-extension and zero-extension pseudocode calls +are left out, due to each operation being different, the above should +be clear that; * the source operands are extended out to the maximum bitwidth of all source operands -- 2.30.2