From f7f30c5ea1b46dc499ce80f0b3ca29fe8702acd1 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 22 Mar 2023 17:36:34 -0700 Subject: [PATCH] duplicate fcvt[f/t]g[o] sections in preperation for splitting out Single versions --- openpower/sv/int_fp_mv.mdwn | 224 ++++++++++++++++++++++++++++++++++ openpower/sv/rfc/ls006.mdwn | 231 ++++++++++++++++++++++++++++++++++++ 2 files changed, 455 insertions(+) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 50fb1e2b7..7d61e16bb 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -470,6 +470,83 @@ Special Registers altered: | `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1, 2` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3, 2` | | `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` | | `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` | +## Floating-point Convert From GPR + +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form | +|-----|------|-------|-------|-------|-------|-------|--------| +| PO | FRT | IT | 0 | RB | XO | RCS | X-Form | + +`fcvtfg FRT, RB, IT, RCS` + +``` + if IT[0] = 0 and RCS[0] = 0 then # 32-bit int -> 64-bit float + # rounding never necessary, so don't touch FPSCR + # based off xvcvsxwdp + if IT = 0 then # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + else # IT = 1 -- Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + FRT <- bfp64_CONVERT_FROM_BFP(src) + else + # rounding may be necessary. based off xscvuxdsp + reset_xflags() + switch(IT) + case(0): # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + case(1): # Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + case(2): # Signed 64-bit + src <- bfp_CONVERT_FROM_SI64((RB)) + default: # Unsigned 64-bit + src <- bfp_CONVERT_FROM_UI64((RB)) + if RCS[0] = 1 then # Single + rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src) + result32 <- bfp32_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP32(result32) + result <- DOUBLE(result32) + else + rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src) + result <- bfp64_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP64(result) + + if xx_flag = 1 then SetFX(FPSCR.XX) + + FRT <- result + FPSCR.FPRF <- cls + FPSCR.FR <- inc_flag + FPSCR.FI <- xx_flag +``` + + +Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit +float in FRT, following the usual 32-bit float in 64-bit float format. +If converting from a unsigned/signed 32-bit integer to a 64-bit float, +rounding is never necessary, so `FPSCR` is unmodified and exceptions are +never raised. Otherwise, `FPSCR` is modified and exceptions are raised +as usual. + +Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point +operations. + +Special Registers altered: + + CR1 (if Rc=1) + FPCSR (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0) + +### Assembly Aliases + +| Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction | +|----------------------|------------------------|------|----------------------|------------------------| +| `fcvtfgw FRT, RB` | `fcvtfg FRT, RB, 0, 0` | | `fcvtfgd FRT, RB` | `fcvtfg FRT, RB, 2, 0` | +| `fcvtfgw. FRT, RB` | `fcvtfg FRT, RB, 0, 1` | | `fcvtfgd. FRT, RB` | `fcvtfg FRT, RB, 2, 1` | +| `fcvtfgws FRT, RB` | `fcvtfg FRT, RB, 0, 2` | | `fcvtfgds FRT, RB` | `fcvtfg FRT, RB, 2, 2` | +| `fcvtfgws. FRT, RB` | `fcvtfg FRT, RB, 0, 3` | | `fcvtfgds. FRT, RB` | `fcvtfg FRT, RB, 2, 3` | +| `fcvtfguw FRT, RB` | `fcvtfg FRT, RB, 1, 0` | | `fcvtfgud FRT, RB` | `fcvtfg FRT, RB, 3, 0` | +| `fcvtfguw. FRT, RB` | `fcvtfg FRT, RB, 1, 1` | | `fcvtfgud. FRT, RB` | `fcvtfg FRT, RB, 3, 1` | +| `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1, 2` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3, 2` | +| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` | | `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` | + ## Floating-point to Integer Conversion Overview
@@ -750,3 +827,150 @@ For brevity, `[o]` is used to mean `o` is optional there. | `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | | `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | | `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | + +## Floating-point Convert To GPR + +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|--------|----|--------|---------| +| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | + +`fcvttg RT, FRB, CVM, IT, RCS` +`fcvttgo RT, FRB, CVM, IT, RCS` + +``` + # based on xscvdpuxws + reset_xflags() + if RCS[0] = 1 then # if Single mode + src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) + else + src <- bfp_CONVERT_FROM_BFP64((FRB)) + + switch(IT) + case(0): # Signed 32-bit + range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) + range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(1): # Unsigned 32-bit + range_min <- bfp_CONVERT_FROM_UI32(0) + range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(2): # Signed 64-bit + range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) + range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + default: # Unsigned 64-bit + range_min <- bfp_CONVERT_FROM_UI64(0) + range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + + if CVM[2] = 1 or FPSCR.RN = 0b01 then + rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src) + else if FPSCR.RN = 0b00 then + rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src) + else if FPSCR.RN = 0b10 then + rnd <- bfp_ROUND_TO_INTEGER_CEIL(src) + else if FPSCR.RN = 0b11 then + rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src) + + switch(CVM) + case(0, 1): # OpenPower semantics + if IsNaN(rnd) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + case(2, 3): # Java/Saturating semantics + if IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + default: # JavaScript semantics + # CVM = 6, 7 are illegal instructions + # this works because the largest type we try to convert from has + # 53 significand bits, and the largest type we try to convert to + # has 64 bits, and the sum of those is strictly less than the 128 + # bits of the intermediate result. + limit <- bfp_CONVERT_FROM_UI128([1] * 128) + if IsInf(rnd) or IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then + result <- [0] * 64 + else + result128 <- si128_CONVERT_FROM_BFP(rnd) + result <- result128[64:127] & js_mask + + switch(IT) + case(0): # Signed 32-bit + result <- EXTS64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63]) + case(1): # Unsigned 32-bit + result <- EXTZ64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63]) + case(2): # Signed 64-bit + result_bfp <- bfp_CONVERT_FROM_SI64(result) + default: # Unsigned 64-bit + result_bfp <- bfp_CONVERT_FROM_UI64(result) + + if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN) + if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI) + if xx_flag = 1 then SetFX(FPSCR.XX) + + vx_flag <- vxsnan_flag | vxcvi_flag + vex_flag <- FPSCR.VE & vx_flag + + if vex_flag = 0 then + RT <- result + FPSCR.FPRF <- undefined + FPSCR.FR <- inc_flag + FPSCR.FI <- xx_flag + if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + else + FPSCR.FR <- 0 + FPSCR.FI <- 0 +``` + +Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +in RT, with the conversion overflow/rounding semantics following the +chosen `CVM` value, following the usual 32-bit float in 64-bit float +format. `FPSCR` is modified and exceptions are raised as usual. + +Both of these instructions have an Rc=1 mode which sets CR0 in the normal +way for any instructions producing a GPR result. Additionally, when OE=1, +if the numerical value of the FP number is not 100% accurately preserved +(due to truncation or saturation and including when the FP number was +NaN) then this is considered to be an integer Overflow condition, and +CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions +that overflow. + +Special Registers altered: + + CR0 (if Rc=1) + XER SO, OV, OV32 (if OE=1) + FPCSR (TODO: which bits?) + +### Assembly Aliases + +For brevity, `[o]` is used to mean `o` is optional there. + +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|------------------------------|--------------------------------|------------------------------|--------------------------------| +| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | +| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | +| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | +| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | +| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | +| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | +| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | +| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index c007cf2fc..c82e991a7 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -318,6 +318,86 @@ Special Registers altered: | `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1, 2` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3, 2` | | `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` | | `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` | +---------- + +\newpage{} + +## Floating-point Convert From GPR + +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30-31 | Form | +|-----|------|-------|-------|-------|-------|-------|--------| +| PO | FRT | IT | 0 | RB | XO | RCS | X-Form | + +`fcvtfg FRT, RB, IT, RCS` + +``` + if IT[0] = 0 and RCS[0] = 0 then # 32-bit int -> 64-bit float + # rounding never necessary, so don't touch FPSCR + # based off xvcvsxwdp + if IT = 0 then # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + else # IT = 1 -- Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + FRT <- bfp64_CONVERT_FROM_BFP(src) + else + # rounding may be necessary. based off xscvuxdsp + reset_xflags() + switch(IT) + case(0): # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + case(1): # Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + case(2): # Signed 64-bit + src <- bfp_CONVERT_FROM_SI64((RB)) + default: # Unsigned 64-bit + src <- bfp_CONVERT_FROM_UI64((RB)) + if RCS[0] = 1 then # Single + rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src) + result32 <- bfp32_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP32(result32) + result <- DOUBLE(result32) + else + rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src) + result <- bfp64_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP64(result) + + if xx_flag = 1 then SetFX(FPSCR.XX) + + FRT <- result + FPSCR.FPRF <- cls + FPSCR.FR <- inc_flag + FPSCR.FI <- xx_flag +``` + + +Convert from a unsigned/signed 32/64-bit integer in RB to a 32/64-bit +float in FRT, following the usual 32-bit float in 64-bit float format. +If converting from a unsigned/signed 32-bit integer to a 64-bit float, +rounding is never necessary, so `FPSCR` is unmodified and exceptions are +never raised. Otherwise, `FPSCR` is modified and exceptions are raised +as usual. + +Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point +operations. + +Special Registers altered: + + CR1 (if Rc=1) + FPCSR (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0) + +### Assembly Aliases + +| Assembly Alias | Full Instruction | | Assembly Alias | Full Instruction | +|----------------------|------------------------|------|----------------------|------------------------| +| `fcvtfgw FRT, RB` | `fcvtfg FRT, RB, 0, 0` | | `fcvtfgd FRT, RB` | `fcvtfg FRT, RB, 2, 0` | +| `fcvtfgw. FRT, RB` | `fcvtfg FRT, RB, 0, 1` | | `fcvtfgd. FRT, RB` | `fcvtfg FRT, RB, 2, 1` | +| `fcvtfgws FRT, RB` | `fcvtfg FRT, RB, 0, 2` | | `fcvtfgds FRT, RB` | `fcvtfg FRT, RB, 2, 2` | +| `fcvtfgws. FRT, RB` | `fcvtfg FRT, RB, 0, 3` | | `fcvtfgds. FRT, RB` | `fcvtfg FRT, RB, 2, 3` | +| `fcvtfguw FRT, RB` | `fcvtfg FRT, RB, 1, 0` | | `fcvtfgud FRT, RB` | `fcvtfg FRT, RB, 3, 0` | +| `fcvtfguw. FRT, RB` | `fcvtfg FRT, RB, 1, 1` | | `fcvtfgud. FRT, RB` | `fcvtfg FRT, RB, 3, 1` | +| `fcvtfguws FRT, RB` | `fcvtfg FRT, RB, 1, 2` | | `fcvtfguds FRT, RB` | `fcvtfg FRT, RB, 3, 2` | +| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` | | `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` | ---------- @@ -616,6 +696,157 @@ For brevity, `[o]` is used to mean `o` is optional there. \newpage{} +## Floating-point Convert To GPR + +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|--------|----|--------|---------| +| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | + +`fcvttg RT, FRB, CVM, IT, RCS` +`fcvttgo RT, FRB, CVM, IT, RCS` + +``` + # based on xscvdpuxws + reset_xflags() + if RCS[0] = 1 then # if Single mode + src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) + else + src <- bfp_CONVERT_FROM_BFP64((FRB)) + + switch(IT) + case(0): # Signed 32-bit + range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) + range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(1): # Unsigned 32-bit + range_min <- bfp_CONVERT_FROM_UI32(0) + range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(2): # Signed 64-bit + range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) + range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + default: # Unsigned 64-bit + range_min <- bfp_CONVERT_FROM_UI64(0) + range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + + if CVM[2] = 1 or FPSCR.RN = 0b01 then + rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src) + else if FPSCR.RN = 0b00 then + rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src) + else if FPSCR.RN = 0b10 then + rnd <- bfp_ROUND_TO_INTEGER_CEIL(src) + else if FPSCR.RN = 0b11 then + rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src) + + switch(CVM) + case(0, 1): # OpenPower semantics + if IsNaN(rnd) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + case(2, 3): # Java/Saturating semantics + if IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + default: # JavaScript semantics + # CVM = 6, 7 are illegal instructions + # this works because the largest type we try to convert from has + # 53 significand bits, and the largest type we try to convert to + # has 64 bits, and the sum of those is strictly less than the 128 + # bits of the intermediate result. + limit <- bfp_CONVERT_FROM_UI128([1] * 128) + if IsInf(rnd) or IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then + result <- [0] * 64 + else + result128 <- si128_CONVERT_FROM_BFP(rnd) + result <- result128[64:127] & js_mask + + switch(IT) + case(0): # Signed 32-bit + result <- EXTS64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63]) + case(1): # Unsigned 32-bit + result <- EXTZ64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63]) + case(2): # Signed 64-bit + result_bfp <- bfp_CONVERT_FROM_SI64(result) + default: # Unsigned 64-bit + result_bfp <- bfp_CONVERT_FROM_UI64(result) + + if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN) + if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI) + if xx_flag = 1 then SetFX(FPSCR.XX) + + vx_flag <- vxsnan_flag | vxcvi_flag + vex_flag <- FPSCR.VE & vx_flag + + if vex_flag = 0 then + RT <- result + FPSCR.FPRF <- undefined + FPSCR.FR <- inc_flag + FPSCR.FI <- xx_flag + if IsNaN(src) or not bfp_COMPARE_EQ(src, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + else + FPSCR.FR <- 0 + FPSCR.FI <- 0 +``` + +Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +in RT, with the conversion overflow/rounding semantics following the +chosen `CVM` value, following the usual 32-bit float in 64-bit float +format. `FPSCR` is modified and exceptions are raised as usual. + +Both of these instructions have an Rc=1 mode which sets CR0 in the normal +way for any instructions producing a GPR result. Additionally, when OE=1, +if the numerical value of the FP number is not 100% accurately preserved +(due to truncation or saturation and including when the FP number was +NaN) then this is considered to be an integer Overflow condition, and +CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions +that overflow. + +Special Registers altered: + + CR0 (if Rc=1) + XER SO, OV, OV32 (if OE=1) + FPCSR (TODO: which bits?) + +### Assembly Aliases + +For brevity, `[o]` is used to mean `o` is optional there. + +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|------------------------------|--------------------------------|------------------------------|--------------------------------| +| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | +| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | +| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | +| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | +| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | +| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | +| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | +| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | + +---------- + +\newpage{} + ---------- # Appendices -- 2.30.2