From f7fcaa07df7b3aab124576dec346ae4fa7c6715b Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 2 Aug 2012 19:42:50 +0000 Subject: [PATCH] radeon/llvm: Remove CMOVLOG DAG node --- .../drivers/radeon/AMDGPUISelLowering.cpp | 2 - .../drivers/radeon/AMDGPUISelLowering.h | 2 - .../drivers/radeon/AMDILISelLowering.cpp | 69 +------------------ src/gallium/drivers/radeon/AMDILInstrInfo.td | 1 - .../drivers/radeon/R600ISelLowering.cpp | 6 ++ .../drivers/radeon/R600Instructions.td | 4 +- 6 files changed, 9 insertions(+), 75 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 31676d86237..568c608cc1f 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -89,7 +89,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) case ISD::SDIV: return LowerSDIV(Op, DAG); case ISD::SREM: return LowerSREM(Op, DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); - case ISD::SELECT: return LowerSELECT(Op, DAG); case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); case ISD::BRCOND: return LowerBRCOND(Op, DAG); // AMDGPU DAG lowering @@ -325,7 +324,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const switch (Opcode) { default: return 0; // AMDIL DAG nodes - NODE_NAME_CASE(CMOVLOG); NODE_NAME_CASE(MAD); NODE_NAME_CASE(CALL); NODE_NAME_CASE(UMUL); diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h index c0945cd8dec..359f795369f 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h @@ -95,7 +95,6 @@ private: SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; @@ -109,7 +108,6 @@ enum { // AMDIL ISD Opcodes FIRST_NUMBER = ISD::BUILTIN_OP_END, - CMOVLOG, // 32bit FP Conditional move logical instruction MAD, // 32bit Fused Multiply Add instruction VBUILD, // scalar to vector mov instruction CALL, // Function call based on a single integer diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index 1dd1b83120a..6983b40a780 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -37,57 +37,6 @@ using namespace llvm; //===----------------------------------------------------------------------===// #include "AMDGPUGenCallingConv.inc" -//===----------------------------------------------------------------------===// -// TargetLowering Implementation Help Functions Begin -//===----------------------------------------------------------------------===// -namespace llvm { -namespace AMDGPU { - static SDValue -getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) -{ - DebugLoc DL = Src.getDebugLoc(); - EVT svt = Src.getValueType().getScalarType(); - EVT dvt = Dst.getValueType().getScalarType(); - if (svt.isFloatingPoint() && dvt.isFloatingPoint()) { - if (dvt.bitsGT(svt)) { - Src = DAG.getNode(ISD::FP_EXTEND, DL, dvt, Src); - } else if (svt.bitsLT(svt)) { - Src = DAG.getNode(ISD::FP_ROUND, DL, dvt, Src, - DAG.getConstant(1, MVT::i32)); - } - } else if (svt.isInteger() && dvt.isInteger()) { - if (!svt.bitsEq(dvt)) { - Src = DAG.getSExtOrTrunc(Src, DL, dvt); - } - } else if (svt.isInteger()) { - unsigned opcode = (asType) ? ISD::BITCAST : ISD::SINT_TO_FP; - if (!svt.bitsEq(dvt)) { - if (dvt.getSimpleVT().SimpleTy == MVT::f32) { - Src = DAG.getSExtOrTrunc(Src, DL, MVT::i32); - } else if (dvt.getSimpleVT().SimpleTy == MVT::f64) { - Src = DAG.getSExtOrTrunc(Src, DL, MVT::i64); - } else { - assert(0 && "We only support 32 and 64bit fp types"); - } - } - Src = DAG.getNode(opcode, DL, dvt, Src); - } else if (dvt.isInteger()) { - unsigned opcode = (asType) ? ISD::BITCAST : ISD::FP_TO_SINT; - if (svt.getSimpleVT().SimpleTy == MVT::f32) { - Src = DAG.getNode(opcode, DL, MVT::i32, Src); - } else if (svt.getSimpleVT().SimpleTy == MVT::f64) { - Src = DAG.getNode(opcode, DL, MVT::i64, Src); - } else { - assert(0 && "We only support 32 and 64bit fp types"); - } - Src = DAG.getSExtOrTrunc(Src, DL, dvt); - } - return Src; -} - -} // End namespace AMDPGU -} // End namespace llvm - //===----------------------------------------------------------------------===// // TargetLowering Implementation Help Functions End //===----------------------------------------------------------------------===// @@ -168,7 +117,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() setOperationAction(ISD::BRIND, VT, Expand); // TODO: Implement custom UREM/SREM routines setOperationAction(ISD::SREM, VT, Expand); - setOperationAction(ISD::SELECT, VT, Custom); setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); if (VT != MVT::i64 && VT != MVT::v2i64) { @@ -220,7 +168,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() setOperationAction(ISD::SMUL_LOHI, VT, Expand); // setOperationAction(ISD::VSETCC, VT, Expand); setOperationAction(ISD::SELECT_CC, VT, Expand); - setOperationAction(ISD::SELECT, VT, Expand); } if (STM.device()->isSupported(AMDGPUDeviceInfo::LongOps)) { @@ -469,20 +416,6 @@ AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const return Nodes1; } -SDValue -AMDGPUTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const -{ - SDValue Cond = Op.getOperand(0); - SDValue LHS = Op.getOperand(1); - SDValue RHS = Op.getOperand(2); - DebugLoc DL = Op.getDebugLoc(); - Cond = AMDGPU::getConversionNode(DAG, Cond, Op, true); - Cond = DAG.getNode(AMDGPUISD::CMOVLOG, - DL, - Op.getValueType(), Cond, LHS, RHS); - return Cond; -} - SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const { @@ -625,7 +558,7 @@ AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); } // jq = (cv ? jq : 0); - jq = DAG.getNode(AMDGPUISD::CMOVLOG, DL, OVT, cv, jq, + jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq, DAG.getConstant(0, OVT)); // dst = iq + jq; iq = DAG.getSExtOrTrunc(iq, DL, OVT); diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td index 5947192048e..b2a0541ae3f 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.td +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td @@ -115,7 +115,6 @@ def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone, // Instructions //===--------------------------------------------------------------------===// // Floating point math functions -def IL_cmov_logical : SDNode<"AMDGPUISD::CMOVLOG", SDTIL_GenTernaryOp>; def IL_div_inf : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>; def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>; diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 768c7db3140..4d8c928f49b 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -426,6 +426,12 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const // SELECT_CC operations. SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); + // Convert floating point condition to i1 + if (VT == MVT::f32) { + Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32, + DAG.getNode(ISD::FNEG, DL, VT, Cond)); + } + return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); } diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index f04fd63882a..c96bc40eaf6 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -450,7 +450,7 @@ def SETGE_UINT : R600_2OP < def CNDE_INT : R600_3OP < 0x1C, "CNDE_INT", [(set (i32 R600_Reg32:$dst), - (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] + (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] >; /* Texture instructions */ @@ -545,7 +545,7 @@ class MULADD_Common inst> : R600_3OP < class CNDE_Common inst> : R600_3OP < inst, "CNDE", [(set (f32 R600_Reg32:$dst), - (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] + (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))] >; class CNDGT_Common inst> : R600_3OP < -- 2.30.2