From f80da65799c366edb88e20ec4f95f60c62ac3d94 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 3 Jun 2020 11:26:33 +1000 Subject: [PATCH] core: Double the dcache and icache sizes This makes the dcache and icache both be 8kB. This still only uses one BRAM per way per cache on the Artix-7, since the BRAMs were only half-used previously. Signed-off-by: Paul Mackerras --- core.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core.vhdl b/core.vhdl index 5517959..4d84b4a 100644 --- a/core.vhdl +++ b/core.vhdl @@ -195,7 +195,7 @@ begin generic map( SIM => SIM, LINE_SIZE => 64, - NUM_LINES => 32, + NUM_LINES => 64, NUM_WAYS => 2 ) port map( @@ -335,7 +335,7 @@ begin dcache_0: entity work.dcache generic map( LINE_SIZE => 64, - NUM_LINES => 32, + NUM_LINES => 64, NUM_WAYS => 2 ) port map ( -- 2.30.2