From f822d2527eda821d7faeab8370a896d4591a100d Mon Sep 17 00:00:00 2001 From: Zack Weinberg Date: Wed, 18 Aug 2004 17:05:14 +0000 Subject: [PATCH] rtl.def (NIL): Delete. * rtl.def (NIL): Delete. * read-rtl.c (read_rtx): Handle (nil) like (define_constants). Tighten the syntax a little. * cfgloop.h, combine.c, cse.c, loop-iv.c, postreload.c, reload.c * config/alpha/alpha.c, config/alpha/alpha.h, config/arc/arc.h * config/arm/arm.h, config/frv/frv.h, config/i386/i386.c * config/i386/predicates.md, config/m32r/m32r.h * config/m68hc11/m68hc11.c, config/mcore/mcore.h, config/mips/mips.c * config/mmix/mmix.c, config/pa/pa.h, config/sh/sh.h * config/sparc/sparc.h, doc/tm.texi: Replace all occurrences of NIL with UNKNOWN. From-SVN: r86193 --- gcc/ChangeLog | 15 ++++++++++ gcc/cfgloop.h | 4 +-- gcc/combine.c | 30 +++++++++---------- gcc/config/alpha/alpha.c | 12 ++++---- gcc/config/alpha/alpha.h | 2 +- gcc/config/arc/arc.h | 2 +- gcc/config/arm/arm.h | 4 +-- gcc/config/frv/frv.h | 4 +-- gcc/config/i386/i386.c | 46 ++++++++++++++--------------- gcc/config/i386/predicates.md | 6 ++-- gcc/config/m32r/m32r.h | 2 +- gcc/config/m68hc11/m68hc11.c | 10 +++---- gcc/config/mcore/mcore.h | 2 +- gcc/config/mips/mips.c | 2 +- gcc/config/mmix/mmix.c | 6 ++-- gcc/config/pa/pa.h | 2 +- gcc/config/rs6000/rs6000.h | 2 +- gcc/config/sh/sh.h | 4 +-- gcc/config/sparc/sparc.h | 2 +- gcc/cse.c | 2 +- gcc/doc/tm.texi | 8 +++--- gcc/loop-iv.c | 54 +++++++++++++++++------------------ gcc/postreload.c | 12 ++++---- gcc/read-rtl.c | 32 +++++++++++---------- gcc/reload.c | 4 +-- gcc/rtl.def | 5 ---- 26 files changed, 143 insertions(+), 131 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 68e12d9e7c9..bc3d3b2f8ed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2004-08-18 Zack Weinberg + + * rtl.def (NIL): Delete. + * read-rtl.c (read_rtx): Handle (nil) like (define_constants). + Tighten the syntax a little. + + * cfgloop.h, combine.c, cse.c, loop-iv.c, postreload.c, reload.c + * config/alpha/alpha.c, config/alpha/alpha.h, config/arc/arc.h + * config/arm/arm.h, config/frv/frv.h, config/i386/i386.c + * config/i386/predicates.md, config/m32r/m32r.h + * config/m68hc11/m68hc11.c, config/mcore/mcore.h, config/mips/mips.c + * config/mmix/mmix.c, config/pa/pa.h, config/sh/sh.h + * config/sparc/sparc.h, doc/tm.texi: + Replace all occurrences of NIL with UNKNOWN. + 2004-08-18 Zack Weinberg * dojump.c (do_jump ): Do not recursively call diff --git a/gcc/cfgloop.h b/gcc/cfgloop.h index 8ccffd3e84b..c2be07dc8f2 100644 --- a/gcc/cfgloop.h +++ b/gcc/cfgloop.h @@ -330,7 +330,7 @@ extern edge split_loop_bb (basic_block, rtx); If first_special is true, the value in the first iteration is delta + mult * base - If extend = NIL, first_special must be false, delta 0, mult 1 and value is + If extend = UNKNOWN, first_special must be false, delta 0, mult 1 and value is subreg_{mode} (base + i * step) The get_iv_value function can be used to obtain these expressions. @@ -345,7 +345,7 @@ struct rtx_iv see the description above). */ rtx base, step; - /* The type of extend applied to it (SIGN_EXTEND, ZERO_EXTEND or NIL). */ + /* The type of extend applied to it (SIGN_EXTEND, ZERO_EXTEND or UNKNOWN). */ enum rtx_code extend; /* Operations applied in the extended mode. */ diff --git a/gcc/combine.c b/gcc/combine.c index 3db1d7d2502..426b0d775e5 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -4926,7 +4926,7 @@ simplify_if_then_else (rtx x) rtx f = make_compound_operation (false_rtx, SET); rtx cond_op0 = XEXP (cond, 0); rtx cond_op1 = XEXP (cond, 1); - enum rtx_code op = NIL, extend_op = NIL; + enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; enum machine_mode m = mode; rtx z = 0, c1 = NULL_RTX; @@ -5025,7 +5025,7 @@ simplify_if_then_else (rtx x) temp = subst (temp, pc_rtx, pc_rtx, 0, 0); temp = gen_binary (op, m, gen_lowpart (m, z), temp); - if (extend_op != NIL) + if (extend_op != UNKNOWN) temp = simplify_gen_unary (extend_op, mode, temp, m); return temp; @@ -5319,7 +5319,7 @@ simplify_set (rtx x) zero_extend to avoid the reload that would otherwise be required. */ if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) - && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL + && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN && SUBREG_BYTE (src) == 0 && (GET_MODE_SIZE (GET_MODE (src)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) @@ -8285,7 +8285,7 @@ extended_count (rtx x, enum machine_mode mode, int unsignedp) the width of this mode matter. It is assumed that the width of this mode is smaller than or equal to HOST_BITS_PER_WIDE_INT. - If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, + If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper result is simply *PCONST0. @@ -8305,13 +8305,13 @@ merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, if (op0 == AND) const1 &= const0; - /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or + /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or if OP0 is SET. */ - if (op1 == NIL || op0 == SET) + if (op1 == UNKNOWN || op0 == SET) return 1; - else if (op0 == NIL) + else if (op0 == UNKNOWN) op0 = op1, const0 = const1; else if (op0 == op1) @@ -8331,7 +8331,7 @@ merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, const0 += const1; break; case NEG: - op0 = NIL; + op0 = UNKNOWN; break; default: break; @@ -8384,12 +8384,12 @@ merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, const0 &= GET_MODE_MASK (mode); if (const0 == 0 && (op0 == IOR || op0 == XOR || op0 == PLUS)) - op0 = NIL; + op0 = UNKNOWN; else if (const0 == 0 && op0 == AND) op0 = SET; else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) && op0 == AND) - op0 = NIL; + op0 = UNKNOWN; /* ??? Slightly redundant with the above mask, but not entirely. Moving this above means we'd have to sign-extend the mode mask @@ -8423,7 +8423,7 @@ simplify_shift_const (rtx x, enum rtx_code code, unsigned int mode_words = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; /* We form (outer_op (code varop count) (outer_const)). */ - enum rtx_code outer_op = NIL; + enum rtx_code outer_op = UNKNOWN; HOST_WIDE_INT outer_const = 0; rtx const_rtx; int complement_p = 0; @@ -9091,7 +9091,7 @@ simplify_shift_const (rtx x, enum rtx_code code, /* We have now finished analyzing the shift. The result should be a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If - OUTER_OP is non-NIL, it is an operation that needs to be applied + OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied to the result of the shift. OUTER_CONST is the relevant constant, but we must turn off all bits turned off in the shift. @@ -9127,7 +9127,7 @@ simplify_shift_const (rtx x, enum rtx_code code, for the outer operation. So try to do the simplification recursively. */ - if (outer_op != NIL && GET_CODE (x) == code + if (outer_op != UNKNOWN && GET_CODE (x) == code && GET_CODE (XEXP (x, 1)) == CONST_INT) x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), INTVAL (XEXP (x, 1))); @@ -9146,7 +9146,7 @@ simplify_shift_const (rtx x, enum rtx_code code, if (complement_p) x = simplify_gen_unary (NOT, result_mode, x, result_mode); - if (outer_op != NIL) + if (outer_op != UNKNOWN) { if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) outer_const = trunc_int_for_mode (outer_const, result_mode); @@ -10506,7 +10506,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) those bits. 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not - NIL. In that case we know those bits are zeros or ones. We must + UNKNOWN. In that case we know those bits are zeros or ones. We must also be sure that they are the same as the upper bits of op1. We can never remove a SUBREG for a non-equality comparison because diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 6252e888c80..1ecd836a6fa 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -2321,13 +2321,13 @@ alpha_emit_conditional_branch (enum rtx_code code) /* When we are not as concerned about non-finite values, and we are comparing against zero, we can branch directly. */ if (op1 == CONST0_RTX (DFmode)) - cmp_code = NIL, branch_code = code; + cmp_code = UNKNOWN, branch_code = code; else if (op0 == CONST0_RTX (DFmode)) { /* Undo the swap we probably did just above. */ tem = op0, op0 = op1, op1 = tem; branch_code = swap_condition (cmp_code); - cmp_code = NIL; + cmp_code = UNKNOWN; } } else @@ -2347,7 +2347,7 @@ alpha_emit_conditional_branch (enum rtx_code code) { /* Whee. Compare and branch against 0 directly. */ if (op1 == const0_rtx) - cmp_code = NIL, branch_code = code; + cmp_code = UNKNOWN, branch_code = code; /* If the constants doesn't fit into an immediate, but can be generated by lda/ldah, we adjust the argument and @@ -2380,7 +2380,7 @@ alpha_emit_conditional_branch (enum rtx_code code) /* Emit an initial compare instruction, if necessary. */ tem = op0; - if (cmp_code != NIL) + if (cmp_code != UNKNOWN) { tem = gen_reg_rtx (cmp_mode); emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)); @@ -2441,7 +2441,7 @@ alpha_emit_setcc (enum rtx_code code) /* The general case: fold the comparison code to the types of compares that we have, choosing the branch as necessary. */ - cmp_code = NIL; + cmp_code = UNKNOWN; switch (code) { case EQ: case LE: case LT: case LEU: case LTU: @@ -2485,7 +2485,7 @@ alpha_emit_setcc (enum rtx_code code) } /* Emit an initial compare instruction, if necessary. */ - if (cmp_code != NIL) + if (cmp_code != UNKNOWN) { enum machine_mode mode = fp_p ? DFmode : DImode; diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index d2ab9332289..37d53f58f3d 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -1370,7 +1370,7 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) /* Define if loading short immediate values into registers sign extends. */ diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index d615364069d..eefac0ce212 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -1155,7 +1155,7 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0) /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Max number of bytes we can move from memory to memory diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ec924105e1a..135a5743ac6 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2217,11 +2217,11 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) \ (TARGET_THUMB ? ZERO_EXTEND : \ ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ - : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) + : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index b31facf7147..bb960e62d70 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -3089,12 +3089,12 @@ do { \ memory in MODE, an integral mode narrower than a word, set the bits outside of MODE to be either the sign-extension or the zero-extension of the data read. Return `SIGN_EXTEND' for values of MODE for which the insn - sign-extends, `ZERO_EXTEND' for which it zero-extends, and `NIL' for other + sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other modes. This macro is not called with MODE non-integral or with a width greater than or equal to `BITS_PER_WORD', so you may return any value in this case. Do - not define this macro if it would always return `NIL'. On machines where + not define this macro if it would always return `UNKNOWN'. On machines where this macro is defined, you will normally define it as the constant `SIGN_EXTEND' or `ZERO_EXTEND'. */ #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 90807672169..50e56ad5dd7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -6016,7 +6016,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse, { enum rtx_code second_code, bypass_code; ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) + if (bypass_code != UNKNOWN || second_code != UNKNOWN) abort (); code = ix86_fp_compare_code_to_integer (code); mode = CCmode; @@ -7961,7 +7961,7 @@ ix86_fp_compare_code_to_integer (enum rtx_code code) /* Split comparison code CODE into comparisons we can do using branch instructions. BYPASS_CODE is comparison code for branch that will branch around FIRST_CODE and SECOND_CODE. If some of branches - is not required, set value to NIL. + is not required, set value to UNKNOWN. We never require more than two branches. */ void @@ -7970,8 +7970,8 @@ ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code, enum rtx_code *second_code) { *first_code = code; - *bypass_code = NIL; - *second_code = NIL; + *bypass_code = UNKNOWN; + *second_code = UNKNOWN; /* The fcomi comparison sets flags as follows: @@ -8021,8 +8021,8 @@ ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code, } if (!TARGET_IEEE_FP) { - *second_code = NIL; - *bypass_code = NIL; + *second_code = UNKNOWN; + *bypass_code = UNKNOWN; } } @@ -8074,7 +8074,7 @@ ix86_fp_comparison_fcomi_cost (enum rtx_code code) if (!TARGET_CMOVE) return 1024; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return (bypass_code != NIL || second_code != NIL) + 2; + return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2; } /* Return cost of comparison done using sahf operation. @@ -8088,7 +8088,7 @@ ix86_fp_comparison_sahf_cost (enum rtx_code code) if (!TARGET_USE_SAHF && !optimize_size) return 1024; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return (bypass_code != NIL || second_code != NIL) + 3; + return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3; } /* Compute cost of the comparison done using any method. @@ -8132,8 +8132,8 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch, ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); /* Do fcomi/sahf based test when profitable. */ - if ((bypass_code == NIL || bypass_test) - && (second_code == NIL || second_test) + if ((bypass_code == UNKNOWN || bypass_test) + && (second_code == UNKNOWN || second_test) && ix86_fp_comparison_arithmetics_cost (code) > cost) { if (TARGET_CMOVE) @@ -8156,11 +8156,11 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch, /* The FP codes work out to act like unsigned. */ intcmp_mode = fpcmp_mode; code = first_code; - if (bypass_code != NIL) + if (bypass_code != UNKNOWN) *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode, gen_rtx_REG (intcmp_mode, FLAGS_REG), const0_rtx); - if (second_code != NIL) + if (second_code != UNKNOWN) *second_test = gen_rtx_fmt_ee (second_code, VOIDmode, gen_rtx_REG (intcmp_mode, FLAGS_REG), const0_rtx); @@ -8326,7 +8326,7 @@ ix86_fp_jump_nontrivial_p (enum rtx_code code) if (!TARGET_CMOVE) return true; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return bypass_code != NIL || second_code != NIL; + return bypass_code != UNKNOWN || second_code != UNKNOWN; } void @@ -8363,7 +8363,7 @@ ix86_expand_branch (enum rtx_code code, rtx label) /* Check whether we will use the natural sequence with one jump. If so, we can expand jump early. Otherwise delay expansion by creating compound insn to not confuse optimizers. */ - if (bypass_code == NIL && second_code == NIL + if (bypass_code == UNKNOWN && second_code == UNKNOWN && TARGET_CMOVE) { ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1, @@ -8476,8 +8476,8 @@ ix86_expand_branch (enum rtx_code code, rtx label) case LEU: code1 = LTU; code2 = GTU; break; case GEU: code1 = GTU; code2 = LTU; break; - case EQ: code1 = NIL; code2 = NE; break; - case NE: code2 = NIL; break; + case EQ: code1 = UNKNOWN; code2 = NE; break; + case NE: code2 = UNKNOWN; break; default: abort (); @@ -8494,16 +8494,16 @@ ix86_expand_branch (enum rtx_code code, rtx label) ix86_compare_op0 = hi[0]; ix86_compare_op1 = hi[1]; - if (code1 != NIL) + if (code1 != UNKNOWN) ix86_expand_branch (code1, label); - if (code2 != NIL) + if (code2 != UNKNOWN) ix86_expand_branch (code2, label2); ix86_compare_op0 = lo[0]; ix86_compare_op1 = lo[1]; ix86_expand_branch (code3, label); - if (code2 != NIL) + if (code2 != UNKNOWN) emit_label (label2); return; } @@ -8968,7 +8968,7 @@ ix86_expand_int_movcc (rtx operands[]) } } - compare_code = NIL; + compare_code = UNKNOWN; if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT && GET_CODE (ix86_compare_op1) == CONST_INT) { @@ -8985,7 +8985,7 @@ ix86_expand_int_movcc (rtx operands[]) } /* Optimize dest = (op0 < 0) ? -1 : cf. */ - if (compare_code != NIL + if (compare_code != UNKNOWN && GET_MODE (ix86_compare_op0) == GET_MODE (out) && (cf == -1 || ct == -1)) { @@ -9113,12 +9113,12 @@ ix86_expand_int_movcc (rtx operands[]) else { code = reverse_condition (code); - if (compare_code != NIL) + if (compare_code != UNKNOWN) compare_code = reverse_condition (compare_code); } } - if (compare_code != NIL) + if (compare_code != UNKNOWN) { /* notl op1 (if needed) sarl $31, op1 diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 58a7dbc0c83..220b01c81cc 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -671,7 +671,7 @@ { enum rtx_code second_code, bypass_code; ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) + if (bypass_code != UNKNOWN || second_code != UNKNOWN) return 0; code = ix86_fp_compare_code_to_integer (code); } @@ -715,7 +715,7 @@ { enum rtx_code second_code, bypass_code; ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - return (bypass_code == NIL && second_code == NIL); + return (bypass_code == UNKNOWN && second_code == UNKNOWN); } switch (code) { @@ -755,7 +755,7 @@ { enum rtx_code second_code, bypass_code; ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) + if (bypass_code != UNKNOWN || second_code != UNKNOWN) return 0; code = ix86_fp_compare_code_to_integer (code); } diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 2f38e0a725d..948ba2a5685 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1712,7 +1712,7 @@ extern char m32r_punct_chars[256]; /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Max number of bytes we can move from memory diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c index ba58e8b9a10..e719ee17bd5 100644 --- a/gcc/config/m68hc11/m68hc11.c +++ b/gcc/config/m68hc11/m68hc11.c @@ -2782,11 +2782,11 @@ m68hc11_expand_compare_and_branch (enum rtx_code code, rtx op0, rtx op1, break; case EQ: - code1 = NIL; + code1 = UNKNOWN; code2 = NE; break; case NE: - code2 = NIL; + code2 = UNKNOWN; break; default: @@ -2800,14 +2800,14 @@ m68hc11_expand_compare_and_branch (enum rtx_code code, rtx op0, rtx op1, * if (lo(a) < lo(b)) goto true; * false: */ - if (code1 != NIL) + if (code1 != UNKNOWN) m68hc11_expand_compare_and_branch (code1, hi[0], hi[1], label); - if (code2 != NIL) + if (code2 != UNKNOWN) m68hc11_expand_compare_and_branch (code2, hi[0], hi[1], label2); m68hc11_expand_compare_and_branch (code3, lo[0], lo[1], label); - if (code2 != NIL) + if (code2 != UNKNOWN) emit_label (label2); return 0; } diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 3ec2dd7c350..3b78d7fcf1d 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -901,7 +901,7 @@ extern const enum reg_class reg_class_from_letter[]; /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 08e38caa708..148bf27e402 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1515,7 +1515,7 @@ mips_build_integer (struct mips_integer_op *codes, || LUI_OPERAND (value)) { /* The value can be loaded with a single instruction. */ - codes[0].code = NIL; + codes[0].code = UNKNOWN; codes[0].value = value; return 1; } diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c index ae69548a222..6c5a193b227 100644 --- a/gcc/config/mmix/mmix.c +++ b/gcc/config/mmix/mmix.c @@ -2701,12 +2701,12 @@ mmix_output_condition (FILE *stream, rtx x, int reversed) { enum machine_mode cc_mode; - /* Terminated with {NIL, NULL, NULL} */ + /* Terminated with {UNKNOWN, NULL, NULL} */ const struct cc_conv *const convs; }; #undef CCEND -#define CCEND {NIL, NULL, NULL} +#define CCEND {UNKNOWN, NULL, NULL} static const struct cc_conv cc_fun_convs[] = {{ORDERED, "Z", "P"}, @@ -2764,7 +2764,7 @@ mmix_output_condition (FILE *stream, rtx x, int reversed) { if (mode == cc_convs[i].cc_mode) { - for (j = 0; cc_convs[i].convs[j].cc != NIL; j++) + for (j = 0; cc_convs[i].convs[j].cc != UNKNOWN; j++) if (cc == cc_convs[i].convs[j].cc) { const char *mmix_cc diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 588b8059364..aefecd20bb4 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1720,7 +1720,7 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 1f5caaa96fc..4fd677e3876 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2133,7 +2133,7 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Define if loading short immediate values into registers sign extends. */ diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 2a5392a01ab..a66129aef20 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -2929,13 +2929,13 @@ struct sh_args { /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ /* For SHmedia, we can truncate to QImode easier using zero extension. */ /* FP registers can load SImode values, but don't implicitly sign-extend them to DImode. */ #define LOAD_EXTEND_OP(MODE) \ (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ - : (MODE) != SImode ? SIGN_EXTEND : NIL) + : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN) /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index db72f351111..719900b14d7 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -2246,7 +2246,7 @@ do { \ /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly - done, NIL if none. */ + done, UNKNOWN if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. diff --git a/gcc/cse.c b/gcc/cse.c index 15e2dc8e60b..93acbe5695c 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -5123,7 +5123,7 @@ cse_insn (rtx insn, rtx libcall_insn) && (GET_MODE_SIZE (mode) < UNITS_PER_WORD) && GET_MODE_CLASS (mode) == MODE_INT && MEM_P (src) && ! do_not_record - && LOAD_EXTEND_OP (mode) != NIL) + && LOAD_EXTEND_OP (mode) != UNKNOWN) { enum machine_mode tmode; diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 03e0c4a17b2..f3574367493 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -8657,21 +8657,21 @@ bits outside of @var{mem_mode} to be either the sign-extension or the zero-extension of the data read. Return @code{SIGN_EXTEND} for values of @var{mem_mode} for which the insn sign-extends, @code{ZERO_EXTEND} for which it zero-extends, and -@code{NIL} for other modes. +@code{UNKNOWN} for other modes. This macro is not called with @var{mem_mode} non-integral or with a width greater than or equal to @code{BITS_PER_WORD}, so you may return any value in this case. Do not define this macro if it would always return -@code{NIL}. On machines where this macro is defined, you will normally +@code{UNKNOWN}. On machines where this macro is defined, you will normally define it as the constant @code{SIGN_EXTEND} or @code{ZERO_EXTEND}. -You may return a non-@code{NIL} value even if for some hard registers +You may return a non-@code{UNKNOWN} value even if for some hard registers the sign extension is not performed, if for the @code{REGNO_REG_CLASS} of these hard registers @code{CANNOT_CHANGE_MODE_CLASS} returns nonzero when the @var{from} mode is @var{mem_mode} and the @var{to} mode is any integral mode larger than this but not larger than @code{word_mode}. -You must return @code{NIL} if for some hard registers that allow this +You must return @code{UNKNOWN} if for some hard registers that allow this mode, @code{CANNOT_CHANGE_MODE_CLASS} says that they cannot change to @code{word_mode}, but that they can change to another integral mode that is larger then @var{mem_mode} but still smaller than @code{word_mode}. diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c index 0a01f86cb43..a7c43e31508 100644 --- a/gcc/loop-iv.c +++ b/gcc/loop-iv.c @@ -427,7 +427,7 @@ iv_constant (struct rtx_iv *iv, rtx cst, enum machine_mode mode) iv->base = cst; iv->step = const0_rtx; iv->first_special = false; - iv->extend = NIL; + iv->extend = UNKNOWN; iv->extend_mode = iv->mode; iv->delta = const0_rtx; iv->mult = const1_rtx; @@ -448,7 +448,7 @@ iv_subreg (struct rtx_iv *iv, enum machine_mode mode) val = lowpart_subreg (mode, val, iv->extend_mode); iv->base = val; - iv->extend = NIL; + iv->extend = UNKNOWN; iv->mode = iv->extend_mode = mode; iv->delta = const0_rtx; iv->mult = const1_rtx; @@ -461,7 +461,7 @@ iv_subreg (struct rtx_iv *iv, enum machine_mode mode) if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode)) return false; - iv->extend = NIL; + iv->extend = UNKNOWN; iv->mode = mode; iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta, @@ -488,7 +488,7 @@ iv_extend (struct rtx_iv *iv, enum rtx_code extend, enum machine_mode mode) val = simplify_gen_unary (extend, mode, val, iv->extend_mode); iv->base = val; - iv->extend = NIL; + iv->extend = UNKNOWN; iv->mode = iv->extend_mode = mode; iv->delta = const0_rtx; iv->mult = const1_rtx; @@ -498,7 +498,7 @@ iv_extend (struct rtx_iv *iv, enum rtx_code extend, enum machine_mode mode) if (mode != iv->extend_mode) return false; - if (iv->extend != NIL + if (iv->extend != UNKNOWN && iv->extend != extend) return false; @@ -512,7 +512,7 @@ iv_extend (struct rtx_iv *iv, enum rtx_code extend, enum machine_mode mode) static bool iv_neg (struct rtx_iv *iv) { - if (iv->extend == NIL) + if (iv->extend == UNKNOWN) { iv->base = simplify_gen_unary (NEG, iv->extend_mode, iv->base, iv->extend_mode); @@ -539,7 +539,7 @@ iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) rtx arg; /* Extend the constant to extend_mode of the other operand if necessary. */ - if (iv0->extend == NIL + if (iv0->extend == UNKNOWN && iv0->mode == iv0->extend_mode && iv0->step == const0_rtx && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode)) @@ -548,7 +548,7 @@ iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode, iv0->base, iv0->mode); } - if (iv1->extend == NIL + if (iv1->extend == UNKNOWN && iv1->mode == iv1->extend_mode && iv1->step == const0_rtx && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode)) @@ -562,7 +562,7 @@ iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) if (mode != iv1->extend_mode) return false; - if (iv0->extend == NIL && iv1->extend == NIL) + if (iv0->extend == UNKNOWN && iv1->extend == UNKNOWN) { if (iv0->mode != iv1->mode) return false; @@ -574,7 +574,7 @@ iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) } /* Handle addition of constant. */ - if (iv1->extend == NIL + if (iv1->extend == UNKNOWN && iv1->mode == mode && iv1->step == const0_rtx) { @@ -582,7 +582,7 @@ iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op) return true; } - if (iv0->extend == NIL + if (iv0->extend == UNKNOWN && iv0->mode == mode && iv0->step == const0_rtx) { @@ -610,7 +610,7 @@ iv_mult (struct rtx_iv *iv, rtx mby) && GET_MODE (mby) != mode) return false; - if (iv->extend == NIL) + if (iv->extend == UNKNOWN) { iv->base = simplify_gen_binary (MULT, mode, iv->base, mby); iv->step = simplify_gen_binary (MULT, mode, iv->step, mby); @@ -635,7 +635,7 @@ iv_shift (struct rtx_iv *iv, rtx mby) && GET_MODE (mby) != mode) return false; - if (iv->extend == NIL) + if (iv->extend == UNKNOWN) { iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby); iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby); @@ -750,7 +750,7 @@ get_biv_step_1 (rtx insn, rtx reg, return false; *inner_step = const0_rtx; - *extend = NIL; + *extend = UNKNOWN; *inner_mode = outer_mode; *outer_step = const0_rtx; } @@ -770,7 +770,7 @@ get_biv_step_1 (rtx insn, rtx reg, *inner_step = simplify_gen_binary (PLUS, outer_mode, *inner_step, *outer_step); *outer_step = const0_rtx; - *extend = NIL; + *extend = UNKNOWN; } switch (code) @@ -794,7 +794,7 @@ get_biv_step_1 (rtx insn, rtx reg, case SIGN_EXTEND: case ZERO_EXTEND: if (GET_MODE (op0) != *inner_mode - || *extend != NIL + || *extend != UNKNOWN || *outer_step != const0_rtx) abort (); @@ -827,11 +827,11 @@ get_biv_step (rtx reg, rtx *inner_step, enum machine_mode *inner_mode, return false; if (*inner_mode != *outer_mode - && *extend == NIL) + && *extend == UNKNOWN) abort (); if (*inner_mode == *outer_mode - && *extend != NIL) + && *extend != UNKNOWN) abort (); if (*inner_mode == *outer_mode @@ -1207,7 +1207,7 @@ get_iv_value (struct rtx_iv *iv, rtx iteration) val = lowpart_subreg (iv->mode, val, iv->extend_mode); - if (iv->extend == NIL) + if (iv->extend == UNKNOWN) return val; val = simplify_gen_unary (iv->extend, iv->extend_mode, val, iv->mode); @@ -1727,7 +1727,7 @@ simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) else abort (); - simplify_using_initial_values (loop, NIL, &head); + simplify_using_initial_values (loop, UNKNOWN, &head); if (head == aggr) { XEXP (*expr, 0) = aggr; @@ -1753,7 +1753,7 @@ simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr) return; } - if (op != NIL) + if (op != UNKNOWN) abort (); e = loop_preheader_edge (loop); @@ -1901,15 +1901,15 @@ canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1, break; case NE: - if (iv0->extend != NIL - && iv1->extend != NIL + if (iv0->extend != UNKNOWN + && iv1->extend != UNKNOWN && iv0->extend != iv1->extend) return false; signed_p = false; - if (iv0->extend != NIL) + if (iv0->extend != UNKNOWN) signed_p = iv0->extend == SIGN_EXTEND; - if (iv1->extend != NIL) + if (iv1->extend != UNKNOWN) signed_p = iv1->extend == SIGN_EXTEND; break; @@ -2403,7 +2403,7 @@ iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition, goto fail; simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); simplify_using_initial_values (loop, IOR, &desc->infinite); - simplify_using_initial_values (loop, NIL, &desc->niter_expr); + simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); /* Rerun the simplification. Consider code (created by copying loop headers) @@ -2426,7 +2426,7 @@ iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition, goto fail; simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions); simplify_using_initial_values (loop, IOR, &desc->infinite); - simplify_using_initial_values (loop, NIL, &desc->niter_expr); + simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr); if (desc->noloop_assumptions && XEXP (desc->noloop_assumptions, 0) == const_true_rtx) diff --git a/gcc/postreload.c b/gcc/postreload.c index c4ab4f229df..3b15118f329 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -214,7 +214,7 @@ reload_cse_simplify_set (rtx set, rtx insn) cselib_val *val; struct elt_loc_list *l; #ifdef LOAD_EXTEND_OP - enum rtx_code extend_op = NIL; + enum rtx_code extend_op = UNKNOWN; #endif dreg = true_regnum (SET_DEST (set)); @@ -234,7 +234,7 @@ reload_cse_simplify_set (rtx set, rtx insn) the destination must be a register that we can widen. */ if (MEM_P (src) && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD - && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL + && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN && !REG_P (SET_DEST (set))) return 0; #endif @@ -260,7 +260,7 @@ reload_cse_simplify_set (rtx set, rtx insn) if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) { #ifdef LOAD_EXTEND_OP - if (extend_op != NIL) + if (extend_op != UNKNOWN) { HOST_WIDE_INT this_val; @@ -290,7 +290,7 @@ reload_cse_simplify_set (rtx set, rtx insn) else if (REG_P (this_rtx)) { #ifdef LOAD_EXTEND_OP - if (extend_op != NIL) + if (extend_op != UNKNOWN) { this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); this_cost = rtx_cost (this_rtx, SET); @@ -313,7 +313,7 @@ reload_cse_simplify_set (rtx set, rtx insn) { #ifdef LOAD_EXTEND_OP if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD - && extend_op != NIL + && extend_op != UNKNOWN #ifdef CANNOT_CHANGE_MODE_CLASS && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), word_mode, @@ -406,7 +406,7 @@ reload_cse_simplify_operands (rtx insn, rtx testreg) #ifdef LOAD_EXTEND_OP if (MEM_P (op) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD - && LOAD_EXTEND_OP (mode) != NIL) + && LOAD_EXTEND_OP (mode) != UNKNOWN) { rtx set = single_set (insn); diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c index 46ca61a188d..45ff077b078 100644 --- a/gcc/read-rtl.c +++ b/gcc/read-rtl.c @@ -545,12 +545,6 @@ again: read_name (tmp_char, infile); tmp_code = UNKNOWN; - - if (! strcmp (tmp_char, "define_constants")) - { - read_constants (infile, tmp_char); - goto again; - } for (i = 0; i < NUM_RTX_CODE; i++) if (! strcmp (tmp_char, GET_RTX_NAME (i))) { @@ -559,16 +553,24 @@ again: } if (tmp_code == UNKNOWN) - fatal_with_file_and_line (infile, "unknown rtx code `%s'", tmp_char); - - /* (NIL) stands for an expression that isn't there. */ - if (tmp_code == NIL) { - /* Discard the closeparen. */ - while ((c = getc (infile)) && c != ')') - ; - - return 0; + /* (nil) stands for an expression that isn't there. */ + if (! strcmp (tmp_char, "nil")) + { + /* Discard the closeparen. */ + c = read_skip_spaces (infile); + if (c != ')') + fatal_expected_char (infile, ')', c); + return 0; + } + /* (define_constants ...) has special syntax. */ + else if (! strcmp (tmp_char, "define_constants")) + { + read_constants (infile, tmp_char); + goto again; + } + else + fatal_with_file_and_line (infile, "unknown rtx code `%s'", tmp_char); } /* If we end up with an insn expression then we free this space below. */ diff --git a/gcc/reload.c b/gcc/reload.c index 09965110204..b114dc2b148 100644 --- a/gcc/reload.c +++ b/gcc/reload.c @@ -1026,7 +1026,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc, && (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) - && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL) + && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN) #endif #ifdef WORD_REGISTER_OPERATIONS || ((GET_MODE_SIZE (inmode) @@ -2971,7 +2971,7 @@ find_reloads (rtx insn, int replace, int ind_levels, int live_known, && (GET_MODE_SIZE (operand_mode[i]) > GET_MODE_SIZE (GET_MODE (operand))) && INTEGRAL_MODE_P (GET_MODE (operand)) - && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL) + && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN) #endif ) #endif diff --git a/gcc/rtl.def b/gcc/rtl.def index 300d9d50267..8fe6d920fb1 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -84,11 +84,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA /* an expression code name unknown to the reader */ DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) -/* (NIL) is used by rtl reader and printer to represent a null pointer. */ - -DEF_RTL_EXPR(NIL, "nil", "*", RTX_EXTRA) - - /* include a file */ DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) -- 2.30.2