From f826221776ccc5878aa16374597851755a0d94e4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Nov 2021 11:44:07 +0000 Subject: [PATCH] update FU_RW_Pending vectors to multi-dest update Copyright and Attribution notices --- src/soc/scoreboard/fu_wr_pending.py | 44 +++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/src/soc/scoreboard/fu_wr_pending.py b/src/soc/scoreboard/fu_wr_pending.py index ea464dce..0fd8e9cb 100644 --- a/src/soc/scoreboard/fu_wr_pending.py +++ b/src/soc/scoreboard/fu_wr_pending.py @@ -1,14 +1,30 @@ +# (DO NOT REMOVE THESE NOTICES) +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2019, 2020, 2021 Luke Kenneth Casson Leighton +# Part of the Libre-SOC Project. +# Sponsored by NLnet EU Grant No: 825310 and 825322 +# Sponsored by NGI POINTER EU Grant No: 871528 + from nmigen import Elaboratable, Module, Signal +from nmigen.cli import verilog, rtlil class FU_RW_Pend(Elaboratable): """ these are allocated per-FU (horizontally), and are of length reg_count """ - def __init__(self, reg_count, n_src): + def __init__(self, reg_count, n_src, n_dst): self.n_src = n_src + self.n_dst = n_dst self.reg_count = reg_count - self.dest_fwd_i = Signal(reg_count, reset_less=True) + # create dest forwarding array + dst = [] + for i in range(n_dst): + j = i + 1 # name numbering to match dst1/dst2 + dst.append(Signal(reg_count, name="dst%d" % j, reset_less=True)) + self.dst_fwd_i = tuple(dst) + self.dest_fwd_i = self.dst_fwd_i[0] # old API + # create src forwarding array src = [] for i in range(n_src): j = i + 1 # name numbering to match src1/src2 @@ -18,12 +34,34 @@ class FU_RW_Pend(Elaboratable): self.reg_wr_pend_o = Signal(reset_less=True) self.reg_rd_pend_o = Signal(reset_less=True) self.reg_rd_src_pend_o = Signal(n_src, reset_less=True) + self.reg_wr_dst_pend_o = Signal(n_dst, reset_less=True) def elaborate(self, platform): m = Module() - m.d.comb += self.reg_wr_pend_o.eq(self.dest_fwd_i.bool()) + for i in range(self.n_dst): + m.d.comb += self.reg_wr_dst_pend_o[i].eq(self.dst_fwd_i[i].bool()) + m.d.comb += self.reg_wr_pend_o.eq(self.reg_wr_dst_pend_o.bool()) for i in range(self.n_src): m.d.comb += self.reg_rd_src_pend_o[i].eq(self.src_fwd_i[i].bool()) m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src_pend_o.bool()) return m + def __iter__(self): + yield self.reg_wr_pend_o + yield self.reg_rd_pend_o + yield self.reg_rd_src_pend_o + yield self.reg_wr_dst_pend_o + yield from self.dst_fwd_i + yield from self.src_fwd_i + + def ports(self): + return list(self) + +def test_fu_rw_pend(): + dut = FU_RW_Pend(4, 2, 2) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_fu_rw_pend.il", "w") as f: + f.write(vl) + +if __name__ == '__main__': + test_fu_rw_pend() -- 2.30.2