From f827ee65e99ba7b75d6d2d5bd0241162c7cf758e Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Wed, 18 Mar 2020 21:23:43 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
 and RISC-V

---
 40/d18266dee4107915eeca2bb78793c0b0a897d0 | 67 +++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 40/d18266dee4107915eeca2bb78793c0b0a897d0

diff --git a/40/d18266dee4107915eeca2bb78793c0b0a897d0 b/40/d18266dee4107915eeca2bb78793c0b0a897d0
new file mode 100644
index 0000000..add0f81
--- /dev/null
+++ b/40/d18266dee4107915eeca2bb78793c0b0a897d0
@@ -0,0 +1,67 @@
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+From: bugzilla-daemon@libre-riscv.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Wed, 18 Mar 2020 21:23:43 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-186-13-ETBowT7GmJ@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
+References: <bug-186-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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-- 
2.30.2