From f841c9de5b7041043040ec1c68706394fc427995 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 13 Apr 2023 04:43:05 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index a80bdc9d9..b628b437e 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -102,14 +102,15 @@ Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous with Scalar instructions. With this in mind it is critical for implementations to observe Strict Element-Level Program Order at all times. *Any* element is Interruptible and Simple-V has -been carefully designed to ensure that Architectural State is -fully preserved. +been carefully designed to ensure that Architectural State may +be fully preserved regardless of that same State. Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1` but the full SVP64 Architectural State may be saved and -restored through manual copying of `SVSTATE` and the four -REMAP SPRs. Whilst this initially sounds unsafe in reality -all rhat Trap Handlers (and function call stack save/restore) +restored through manual copying of `SVSTATE` (and the four +REMAP SPRs if in use at the time) +Whilst this initially sounds unsafe in reality +all that Trap Handlers (and function call stack save/restore) need do is avoid use of SVP64 Prefixed instructions to perform the necessary save/restore of Simple-V Architectural State. -- 2.30.2