From f861652571128e99299b00100261939078797f49 Mon Sep 17 00:00:00 2001 From: rishucoding Date: Wed, 4 Jul 2018 12:37:11 +0530 Subject: [PATCH] correction in enable and selection lines for twi_scl --- src/test_bsv/tests/test_pinmux.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py index 1650684..3da87a6 100644 --- a/src/test_bsv/tests/test_pinmux.py +++ b/src/test_bsv/tests/test_pinmux.py @@ -50,6 +50,7 @@ def pinmux_gpio2(dut): str(dut.iocell_side_io2_cell_out)) # GPIO2-in test (first see if it's tri-state) + # if str(dut.peripheral_side_gpioa_a2_in) != "x": raise TestFailure( "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" % @@ -128,12 +129,12 @@ def pinmux_twi_scl(dut): # mux selection lines, each input two bit wide dut.mux_lines_cell0_mux_in = 1 dut.mux_lines_cell1_mux_in = 2 - dut.mux_lines_cell2_mux_in = 0 + dut.mux_lines_cell2_mux_in = 2 yield Timer(2) # enable input for mux dut.EN_mux_lines_cell0_mux = 0 - dut.EN_mux_lines_cell1_mux = 1 - dut.EN_mux_lines_cell2_mux = 0 + dut.EN_mux_lines_cell1_mux = 0 + dut.EN_mux_lines_cell2_mux = 1 yield Timer(2) -- 2.30.2