From f87be193878322d7bcc2743d060bb9e3fea12cef Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 29 Jul 2019 07:13:03 -0700 Subject: [PATCH] fix the mess introduced by "fix pipeline stage count" not a pure revert This reverts commit 30a3d1e975cd3df7ea701fdf0fe3bd0ba0757d3e. --- src/ieee754/fpdiv/pipeline.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 3662b215..278e1804 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -163,6 +163,8 @@ class FPDIVMuxInOut(ReservationStations): fmt = FPFormat.standard(width) log2_radix = 3 # tested options so far: 1, 2 and 3. + n_comb_stages = 2 # 2 compute stages per pipeline stage + fraction_width = fmt.fraction_width # extra bits needed: guard + round @@ -173,8 +175,6 @@ class FPDIVMuxInOut(ReservationStations): # the last stage cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix) - n_comb_stages = (cfg.n_stages + 1) // 2 # 2 compute steps per stage - self.pspec.fpformat = fmt self.pspec.n_comb_stages = n_comb_stages self.pspec.core_config = cfg -- 2.30.2