From f88d6a87dbb070ce92b38b9061766f2b3fc29b84 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Apr 2022 12:51:02 +0100 Subject: [PATCH] add verilog-wishbone (for async bridge) to hdl-dev-ls2 --- hdl-dev-ls2 | 1 + 1 file changed, 1 insertion(+) diff --git a/hdl-dev-ls2 b/hdl-dev-ls2 index 34a801a..3e58228 100755 --- a/hdl-dev-ls2 +++ b/hdl-dev-ls2 @@ -14,6 +14,7 @@ git clone https://git.libre-soc.org/git/lambdasoc.git git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi git clone https://github.com/freecores/uart16550 git clone https://github.com/freecores/ethmac +git clone https://github.com/alexforencich/verilog-wishbone ' # lambdasoc -- 2.30.2