From f8928b5031e3442482ad97d7da1633a7883a5f9a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 20 Feb 2022 00:06:56 +0000 Subject: [PATCH] for simulatio keep the simulated dram in the same clock domain as the main sim, for now --- src/ls2.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index f564b46..926256c 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -190,12 +190,19 @@ class DDR3SoC(SoC, Elaboratable): geom_settings=ddrmodule.geom_settings, timing_settings=ddrmodule.timing_settings, clk_freq=clk_freq) - self.dramcore = drs(dramcore) - self._decoder.add(self.dramcore.bus, addr=dramcore_addr) + self._decoder.add(dramcore.bus, addr=dramcore_addr) # map the DRAM onto Wishbone - self.drambone = drs(gramWishbone(self.dramcore)) - self._decoder.add(self.drambone.bus, addr=ddr_addr) + drambone = gramWishbone(dramcore) + self._decoder.add(drambone.bus, addr=ddr_addr) + + # for simulation do not use a separate clock domain (yet) + if fpga == 'sim': + self.dramcore = dramcore + self.drambone = drambone + else: + self.dramcore = drs(dramcore) + self.drambone = drs(drambone) self.memory_map = self._decoder.bus.memory_map -- 2.30.2