From f8ac63a289a4e411e2c1779ef7ee1508de2fd329 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 20 Aug 2019 10:48:52 +0100 Subject: [PATCH] arch-arm: SGI registers undecoded in AArch32 Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612 Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/miscregs.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 87cc3fde3..cad123fcc 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -962,6 +962,18 @@ decodeCP15Reg64(unsigned crm, unsigned opc1) return MISCREG_CNTHP_CVAL; } break; + case 12: + switch (opc1) { + case 0: + return MISCREG_ICC_SGI1R; + case 1: + return MISCREG_ICC_ASGI1R; + case 2: + return MISCREG_ICC_SGI0R; + default: + break; + } + break; case 15: if (opc1 == 0) return MISCREG_CPUMERRSR; -- 2.30.2