From f8ca4018bad7508a5e62bf83ccbf1c574a2544dd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 Apr 2022 18:07:10 +0100 Subject: [PATCH] add pseudocode for weirdaddx and msubx --- openpower/sv/bitmanip/appendix.mdwn | 30 ++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/openpower/sv/bitmanip/appendix.mdwn b/openpower/sv/bitmanip/appendix.mdwn index e79894947..a5f9fcc7f 100644 --- a/openpower/sv/bitmanip/appendix.mdwn +++ b/openpower/sv/bitmanip/appendix.mdwn @@ -122,6 +122,34 @@ may be morphed to: Transformation of 4-in, 2-out into a pair of operations: * 3-in, 2-out `msubx RT, RA, RB, RC` producing {RT,RS} where RS=RT+VL -* 3-in, 2-out `weirdsubx RT, RA, RB` a hidden RS=RT+VL as input *and output* +* 3-in, 2-out `weirdsubx RT, RA, RB` a hidden RS=RT+VL as input, RA dual + +**msubx RT, RA, RB, RC** (RS=RT+VL for SVP64, RS=RT+1 for scalar) + + prod[0:127] = (RA) * (RB) + sub[0:127] = EXTZ(RC) - prod + RT <- sub[64:127] + RS <- sub[0:63] + +**weirdaddx RT, RA, RB** (RS=RT+VL) + + cat[0:127] = (RB) || (RS) + sum[0:127] = cat + EXTZ(RA) + [1]*128 + rhi[0:63] = sum[0:63] + if (RA) <= 1 then rhi = rhi + ([0]*63 || 1) + RA = rhi + RT = sum[64:127] + +These two combine as, simply: + + # RS=RT+VL, assume VL=8, therefore RS starts at r8.v + # q : r16 + # dividend: r24.v + # divisor : r32.v + # carry : r40 + li r40, 0 + sv.msubx r0.v, r16, r24.v, r32.v + sv.weirdaddx r0.v, r40, r8.v + -- 2.30.2