From f8d6b590939bd5b5f127cca037225332a54611e5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 17 Sep 2021 16:13:15 +0100 Subject: [PATCH] update comments https://bugs.libre-soc.org/show_bug.cgi?id=686#c51 --- src/soc/simple/test/test_runner.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 60a8e9df..d1d8e209 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -3,6 +3,7 @@ related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=363 + * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51 """ from nmigen import Module, Signal, Cat, ClockSignal from nmigen.hdl.xfrm import ResetInserter @@ -310,6 +311,12 @@ class TestRunner(FHDLTestCase): yield yield + # TODO, here is where the static (expected) results + # can be checked: register check (TODO, memory check) + # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51 + # yield from check_regs(self, sim, core, test, code, + # >>>expected_data<<<) + # get CR cr = yield from get_dmi(dmi, DBGCore.CR) print("after test %s cr value %x" % (test.name, cr)) -- 2.30.2