From f8dfa2c982addbde7776dbfddc87d2b8c3e247eb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 18:44:23 +0100 Subject: [PATCH] sorting out trap fastregs --- src/soc/decoder/isa/caller.py | 5 ++++- src/soc/decoder/power_decoder2.py | 12 +++++++++++- src/soc/fu/test/common.py | 8 ++++---- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index a57194be..17e9ed94 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -211,7 +211,10 @@ class SPR(dict): if key in self: res = dict.__getitem__(self, key) else: - info = spr_dict[key] + if isinstance(key, int): + info = spr_dict[key] + else: + info = spr_byname[key] dict.__setitem__(self, key, SelectableInt(0, info.length)) res = dict.__getitem__(self, key) print ("spr returning", key, res) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index aa9fcaec..1830c5f7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -312,6 +312,11 @@ class DecodeOut(Elaboratable): comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0 comb += self.fast_out.ok.eq(1) + # TRAP fast1 = SRR0 + with m.If(op.internal_op == InternalOp.OP_TRAP): + comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0 + comb += self.fast_out.ok.eq(1) + return m @@ -351,6 +356,11 @@ class DecodeOut2(Elaboratable): comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1 comb += self.fast_out.ok.eq(1) + # TRAP fast2 = SRR1 + with m.If(op.internal_op == InternalOp.OP_TRAP): + comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1 + comb += self.fast_out.ok.eq(1) + return m @@ -587,7 +597,7 @@ class PowerDecode2(Elaboratable): comb += e.read_fast1.eq(dec_a.fast_out) comb += e.read_fast2.eq(dec_b.fast_out) comb += e.write_fast1.eq(dec_o.fast_out) - comb += e.write_fast1.eq(dec_o2.fast_out) + comb += e.write_fast2.eq(dec_o2.fast_out) comb += e.read_cr1.eq(dec_cr_in.cr_bitfield) comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index bd0e948e..1143e895 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -257,16 +257,16 @@ class ALUHelpers: if ok: spr_num = yield dec2.e.write_fast2.data spr_num = fast_reg_to_spr(spr_num) - spr_name = spr_dict[spr_num] - res['fast2'] = sim.spr[spr_name] + spr_name = spr_dict[spr_num].SPR + res['fast2'] = sim.spr[spr_name].value def get_wr_fast_spr1(res, sim, dec2): ok = yield dec2.e.write_fast1.ok if ok: spr_num = yield dec2.e.write_fast1.data spr_num = fast_reg_to_spr(spr_num) - spr_name = spr_dict[spr_num] - res['fast1'] = sim.spr[spr_name] + spr_name = spr_dict[spr_num].SPR + res['fast1'] = sim.spr[spr_name].value def get_wr_sim_xer_ca(res, sim, dec2): cry_out = yield dec2.e.output_carry -- 2.30.2