From f8e3ba7b7bc7fc974211fe3e908d3e1540e427af Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tiago=20M=C3=BCck?= Date: Mon, 8 Jun 2020 19:01:14 -0500 Subject: [PATCH] mem-ruby: sequencer callback for unique writes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit A controller may complete a write without obtaining a full copy of the line. This patch adds a specific callback for this purpose that prevents reads to be coalesced with a write on a potentially incomplete line. Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31269 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Bradford Beckmann --- src/mem/ruby/protocol/RubySlicc_Types.sm | 1 + src/mem/ruby/system/Sequencer.cc | 12 +++++++++++- src/mem/ruby/system/Sequencer.hh | 10 +++++++++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index b4854d494..a7b9d345b 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -129,6 +129,7 @@ structure (Sequencer, external = "yes") { void writeCallback(Addr, DataBlock, bool, MachineType); void writeCallback(Addr, DataBlock, bool, MachineType, Cycles, Cycles, Cycles); + void writeUniqueCallback(Addr, DataBlock); // ll/sc support void writeCallbackScFail(Addr, DataBlock); diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 0614c1108..6b50636d9 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -352,7 +352,8 @@ Sequencer::writeCallback(Addr address, DataBlock& data, const bool externalHit, const MachineType mach, const Cycles initialRequestTime, const Cycles forwardRequestTime, - const Cycles firstResponseTime) + const Cycles firstResponseTime, + const bool noCoales) { // // Free the whole list as we assume we have had the exclusive access @@ -370,6 +371,15 @@ Sequencer::writeCallback(Addr address, DataBlock& data, int aliased_loads = 0; while (!seq_req_list.empty()) { SequencerRequest &seq_req = seq_req_list.front(); + + if (noCoales && !ruby_request) { + // Do not process follow-up requests + // (e.g. if full line no present) + // Reissue to the cache hierarchy + issueRequest(seq_req.pkt, seq_req.m_second_type); + break; + } + if (ruby_request) { assert(seq_req.m_type != RubyRequestType_LD); assert(seq_req.m_type != RubyRequestType_Load_Linked); diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 4a5e28123..e1a3c2df1 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -103,7 +103,15 @@ class Sequencer : public RubyPort const MachineType mach = MachineType_NUM, const Cycles initialRequestTime = Cycles(0), const Cycles forwardRequestTime = Cycles(0), - const Cycles firstResponseTime = Cycles(0)); + const Cycles firstResponseTime = Cycles(0), + const bool noCoales = false); + + // Write callback that prevents coalescing + void writeUniqueCallback(Addr address, DataBlock& data) + { + writeCallback(address, data, true, MachineType_NUM, Cycles(0), + Cycles(0), Cycles(0), true); + } void readCallback(Addr address, DataBlock& data, -- 2.30.2