From f8e4542bad7dd9bb97b2990947ef74dbb2ee75e4 Mon Sep 17 00:00:00 2001 From: Dylan Baker Date: Fri, 6 Dec 2019 09:20:09 -0800 Subject: [PATCH] replace _mesa_logbase2 with util_logbase2 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Reviewed-by: Kristian H. Kristensen Reviewed-by: Matt Turner Part-of: --- src/intel/compiler/brw_eu_emit.c | 4 ++-- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_generator.cpp | 2 +- src/intel/compiler/brw_fs_reg_allocate.cpp | 4 ++-- src/intel/compiler/brw_ir_fs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_clip.c | 2 +- src/mesa/drivers/dri/i965/brw_vs.c | 2 +- src/mesa/drivers/dri/radeon/radeon_texture.c | 2 +- src/mesa/main/teximage.c | 12 ++++++------ src/mesa/state_tracker/st_cb_texture.c | 2 +- src/util/imports.h | 20 -------------------- 11 files changed, 18 insertions(+), 38 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 83f7f4a62ca..8786903dada 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -593,7 +593,7 @@ gen7_set_dp_scratch_message(struct brw_codegen *p, const struct gen_device_info *devinfo = p->devinfo; assert(num_regs == 1 || num_regs == 2 || num_regs == 4 || (devinfo->gen >= 8 && num_regs == 8)); - const unsigned block_size = (devinfo->gen >= 8 ? _mesa_logbase2(num_regs) : + const unsigned block_size = (devinfo->gen >= 8 ? util_logbase2(num_regs) : num_regs - 1); brw_set_desc(p, inst, brw_message_desc( @@ -3421,7 +3421,7 @@ brw_broadcast(struct brw_codegen *p, /* Take into account the component size and horizontal stride. */ assert(src.vstride == src.hstride + src.width); brw_SHL(p, addr, vec1(idx), - brw_imm_ud(_mesa_logbase2(type_sz(src.type)) + + brw_imm_ud(util_logbase2(type_sz(src.type)) + src.hstride - 1)); /* We can only address up to limit bytes using the indirect diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b578d82a252..0fa0be683f0 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6297,7 +6297,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo, /* Only power-of-two execution sizes are representable in the instruction * control fields. */ - return 1 << _mesa_logbase2(max_width); + return 1 << util_logbase2(max_width); } /** diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index b50f03142b5..d7464c95297 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -587,7 +587,7 @@ fs_generator::generate_shuffle(fs_inst *inst, /* Take into account the component size and horizontal stride. */ assert(src.vstride == src.hstride + src.width); brw_SHL(p, addr, group_idx, - brw_imm_uw(_mesa_logbase2(type_sz(src.type)) + + brw_imm_uw(util_logbase2(type_sz(src.type)) + src.hstride - 1)); /* Add on the register start offset */ diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index 9e79e5faae4..ee758009cad 100644 --- a/src/intel/compiler/brw_fs_reg_allocate.cpp +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp @@ -86,7 +86,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) { const struct gen_device_info *devinfo = compiler->devinfo; int base_reg_count = BRW_MAX_GRF; - const int index = _mesa_logbase2(dispatch_width / 8); + const int index = util_logbase2(dispatch_width / 8); if (dispatch_width > 8 && devinfo->gen >= 7) { /* For IVB+, we don't need the PLN hacks or the even-reg alignment in @@ -423,7 +423,7 @@ public: * for reg_width == 2. */ int reg_width = fs->dispatch_width / 8; - rsi = _mesa_logbase2(reg_width); + rsi = util_logbase2(reg_width); payload_node_count = ALIGN(fs->first_non_payload_grf, reg_width); /* Get payload IP information */ diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index 973c9fb168d..af56753fc38 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -298,8 +298,8 @@ subscript(fs_reg reg, brw_reg_type type, unsigned i) /* The stride is encoded inconsistently for fixed GRF and ARF registers * as the log2 of the actual vertical and horizontal strides. */ - const int delta = _mesa_logbase2(type_sz(reg.type)) - - _mesa_logbase2(type_sz(type)); + const int delta = util_logbase2(type_sz(reg.type)) - + util_logbase2(type_sz(type)); reg.hstride += (reg.hstride ? delta : 0); reg.vstride += (reg.vstride ? delta : 0); diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index 49c41d8c2e4..082724c82d1 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -112,7 +112,7 @@ brw_upload_clip_prog(struct brw_context *brw) key.pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION); /* _NEW_TRANSFORM (also part of VUE map)*/ if (ctx->Transform.ClipPlanesEnabled) - key.nr_userclip = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; + key.nr_userclip = util_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; if (devinfo->gen == 5) key.clip_mode = BRW_CLIP_MODE_KERNEL_CLIP; diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 6ce7a1ce889..b2e8c2225bd 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -265,7 +265,7 @@ brw_vs_populate_key(struct brw_context *brw, (ctx->API == API_OPENGL_COMPAT || ctx->API == API_OPENGLES) && vp->program.info.clip_distance_array_size == 0) { key->nr_userclip_plane_consts = - _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; + util_logbase2(ctx->Transform.ClipPlanesEnabled) + 1; } if (devinfo->gen < 6) { diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index a2c43aa7b5b..3bf7a0dbec3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -681,7 +681,7 @@ static radeon_mipmap_tree *radeon_miptree_create_for_teximage(radeonContextPtr r texImage->Level == firstLevel) { lastLevel = firstLevel; } else { - lastLevel = firstLevel + _mesa_logbase2(MAX2(MAX2(width, height), depth)); + lastLevel = firstLevel + util_logbase2(MAX2(MAX2(width, height), depth)); } } diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index 47220c917cf..986ee614915 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -718,7 +718,7 @@ _mesa_get_tex_max_num_levels(GLenum target, GLsizei width, GLsizei height, return 1; } - return _mesa_logbase2(size) + 1; + return util_logbase2(size) + 1; } @@ -844,7 +844,7 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx, img->Depth = depth; img->Width2 = width - 2 * border; /* == 1 << img->WidthLog2; */ - img->WidthLog2 = _mesa_logbase2(img->Width2); + img->WidthLog2 = util_logbase2(img->Width2); switch(target) { case GL_TEXTURE_1D: @@ -887,7 +887,7 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx, case GL_TEXTURE_2D_MULTISAMPLE: case GL_PROXY_TEXTURE_2D_MULTISAMPLE: img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */ - img->HeightLog2 = _mesa_logbase2(img->Height2); + img->HeightLog2 = util_logbase2(img->Height2); if (depth == 0) img->Depth2 = 0; else @@ -901,16 +901,16 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx, case GL_TEXTURE_2D_MULTISAMPLE_ARRAY: case GL_PROXY_TEXTURE_2D_MULTISAMPLE_ARRAY: img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */ - img->HeightLog2 = _mesa_logbase2(img->Height2); + img->HeightLog2 = util_logbase2(img->Height2); img->Depth2 = depth; /* no border */ img->DepthLog2 = 0; /* not used */ break; case GL_TEXTURE_3D: case GL_PROXY_TEXTURE_3D: img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */ - img->HeightLog2 = _mesa_logbase2(img->Height2); + img->HeightLog2 = util_logbase2(img->Height2); img->Depth2 = depth - 2 * border; /* == 1 << img->DepthLog2; */ - img->DepthLog2 = _mesa_logbase2(img->Depth2); + img->DepthLog2 = util_logbase2(img->Depth2); break; default: _mesa_problem(NULL, "invalid target 0x%x in _mesa_init_teximage_fields()", diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 5742fb591ca..c688680a268 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -3065,7 +3065,7 @@ st_TestProxyTexImage(struct gl_context *ctx, GLenum target, } else { /* assume a full set of mipmaps */ - pt.last_level = _mesa_logbase2(MAX3(width, height, depth)); + pt.last_level = util_logbase2(MAX3(width, height, depth)); } return pipe->screen->can_create_resource(pipe->screen, &pt); diff --git a/src/util/imports.h b/src/util/imports.h index 22364c68840..67254a030a8 100644 --- a/src/util/imports.h +++ b/src/util/imports.h @@ -191,26 +191,6 @@ static inline int IFLOOR(float f) } -/* - * Returns the floor form of binary logarithm for a 32-bit integer. - */ -static inline unsigned -_mesa_logbase2(unsigned n) -{ -#ifdef HAVE___BUILTIN_CLZ - return (31 - __builtin_clz(n | 1)); -#else - unsigned pos = 0; - if (n >= 1<<16) { n >>= 16; pos += 16; } - if (n >= 1<< 8) { n >>= 8; pos += 8; } - if (n >= 1<< 4) { n >>= 4; pos += 4; } - if (n >= 1<< 2) { n >>= 2; pos += 2; } - if (n >= 1<< 1) { pos += 1; } - return pos; -#endif -} - - /********************************************************************** * Functions */ -- 2.30.2