From f8f5483a47a94da8cca64d8ddf1f2bbfa449c905 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 11 Mar 2018 07:06:13 +0000 Subject: [PATCH] --- shakti/m_class/pinmux.mdwn | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn index fe415be90..f55c32ef4 100644 --- a/shakti/m_class/pinmux.mdwn +++ b/shakti/m_class/pinmux.mdwn @@ -6,6 +6,7 @@ is a Watchdog Timer and others. * Pinmux ("IOF") for multiplexing several I/O functions onto a single pin +* - implementation by Shakti RISE Group Surprisingly complex! @@ -18,16 +19,20 @@ optional pull-up and pull-down resistors, in an IDENTICAL fashion to that of ALL major well-known embedded SoCs from ST Micro, Cypress, Texas Instruments, NXP, Rockchip, Allwinner and many many others". +* The IO pad shall have pull-up enable, pull-down enable, variable + frequency de-bounce (schmidt trigger), tri-state capability, + variable current drive (on input), Open Drain and CMOS Push-Push. +* Certain functions shall have the ability to control whether + IO pads will be input or output (not the GPIO registers). * Number of wires shall be minimised especially in cases where the IO pad (puen, oe) need to change under the control of the function (not the GPIO registers). -* There shall be no short-circuits created by multiple input - pins trying to drive the same input function -* The IO pad shall have pull-up enable, pull-down enable, variable - frequency de-bounce, tri-state capability, Open Drain and CMOS - Push-Push. * The amount of latency (gates in between I/O pad and function) shall be minimised +* There shall be no short-circuits created by multiple input + pins trying to drive the same input function +* There shall be no short-circuits even when functions control + when the IO pad is an input. ## Analysis -- 2.30.2