From f903da7335433ae243cf7ff59662be1a03ee9a14 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 7 May 2012 14:52:11 -0400 Subject: [PATCH] radeon/llvm: Add some comments and fix coding style --- src/gallium/drivers/radeon/AMDGPU.h | 37 ++++++++----------- .../drivers/radeon/AMDGPUConvertToISA.cpp | 2 +- .../drivers/radeon/AMDGPUISelLowering.cpp | 4 +- .../drivers/radeon/AMDGPUISelLowering.h | 5 ++- src/gallium/drivers/radeon/AMDGPUInstrInfo.h | 21 ++++++----- .../radeon/AMDGPULowerInstructions.cpp | 5 ++- .../drivers/radeon/AMDGPURegisterInfo.cpp | 4 +- .../drivers/radeon/AMDGPUTargetMachine.cpp | 5 ++- 8 files changed, 41 insertions(+), 42 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h index 7aeb3a8e625..ab26dc98f93 100644 --- a/src/gallium/drivers/radeon/AMDGPU.h +++ b/src/gallium/drivers/radeon/AMDGPU.h @@ -1,4 +1,4 @@ -//===-- AMDGPU.h - TODO: Add brief description -------===// +//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -6,10 +6,6 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// TODO: Add full description -// -//===----------------------------------------------------------------------===// #ifndef AMDGPU_H #define AMDGPU_H @@ -19,25 +15,24 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { - class FunctionPass; - class AMDGPUTargetMachine; - - FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS); - FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm); - FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm); - FunctionPass *createSIInitMachineFunctionInfoPass(TargetMachine &tm); - FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm); - FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm); - FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); +class FunctionPass; +class AMDGPUTargetMachine; - FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm); +// R600 Passes +FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS); +FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm); - FunctionPass *createAMDGPUDelimitInstGroupsPass(TargetMachine &tm); +// SI Passes +FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm); +FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm); +FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm); +FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); - FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm); +// Passes common to R600 and SI +FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm); +FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm); - FunctionPass *createAMDGPUFixRegClassesPass(TargetMachine &tm); +} // End namespace llvm -} /* End namespace llvm */ -#endif /* AMDGPU_H */ +#endif // AMDGPU_H diff --git a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp index ce947f8ff78..8e82b8438bb 100644 --- a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp +++ b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp @@ -34,7 +34,7 @@ namespace { virtual bool runOnMachineFunction(MachineFunction &MF); }; -} /* End anonymous namespace */ +} // End anonymous namespace char AMDGPUConvertToISAPass::ID = 0; diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 2c1052fd8ea..2bdc8a759f2 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPUISelLowering.cpp - TODO: Add brief description -------===// +//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// This is the parent TargetLowering class for hardware code gen targets. // //===----------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h index 3c5beb1cdae..1b3f71006e2 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h @@ -1,4 +1,4 @@ -//===-- AMDGPUISelLowering.h - TODO: Add brief description -------===// +//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// This file contains the interface defintiion of the TargetLowering class +// that is common to all AMD GPUs. // //===----------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h index ad135d46cb3..930b41e7191 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h @@ -1,4 +1,4 @@ -//===-- AMDGPUInstrInfo.h - TODO: Add brief description -------===// +//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// This file contains the definitoin of a TargetInstrInfo class that is common +// to all AMD GPUs. // //===----------------------------------------------------------------------===// @@ -21,17 +22,17 @@ namespace llvm { - class AMDGPUTargetMachine; - class MachineFunction; - class MachineInstr; - class MachineInstrBuilder; +class AMDGPUTargetMachine; +class MachineFunction; +class MachineInstr; +class MachineInstrBuilder; - class AMDGPUInstrInfo : public AMDILInstrInfo { - private: +class AMDGPUInstrInfo : public AMDILInstrInfo { +private: AMDGPUTargetMachine & TM; std::map amdilToISA; - public: +public: explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm); virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; @@ -42,7 +43,7 @@ namespace llvm { DebugLoc DL) const; #include "AMDGPUInstrEnums.h.include" - }; +}; } // End llvm namespace diff --git a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp index b138e2bb928..2e455fea8ab 100644 --- a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp +++ b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPULowerInstructions.cpp - TODO: Add brief description -------===// +//===-- AMDGPULowerInstructions.cpp - AMDGPU lowering pass ----------------===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// This pass lowers unsupported AMDIL MachineInstrs to LLVM pseudo +// MachineInstrs for hw codegen targets. // //===----------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp b/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp index 162a49116a0..ad48335fd33 100644 --- a/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPURegisterInfo.cpp - TODO: Add brief description -------===// +//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// Parent TargetRegisterInfo class common to all hw codegen targets. // //===----------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp index 5621d58e0d3..5046418b0ec 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPUTargetMachine.cpp - TODO: Add brief description -------===// +//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// TODO: Add full description +// The AMDGPU target machine contains all of the hardware specific information +// needed to emit code for R600 and SI GPUs. // //===----------------------------------------------------------------------===// -- 2.30.2