From f9049fbf025bf2a8c97d5c8f70c3623cbb32074b Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 4 Mar 2021 20:16:50 +0100 Subject: [PATCH] update test_caller_radix.py --- src/soc/decoder/isa/test_caller_radix.py | 26 ++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py index 52928500..9b92cf81 100644 --- a/src/soc/decoder/isa/test_caller_radix.py +++ b/src/soc/decoder/isa/test_caller_radix.py @@ -1,7 +1,7 @@ from nmigen import Module, Signal #from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase -#import unittest +import unittest from soc.decoder.isa.caller import ISACaller from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) @@ -10,8 +10,26 @@ from soc.decoder.isa.caller import ISACaller, inject, RADIX from soc.decoder.selectable_int import SelectableInt from soc.decoder.orderedset import OrderedSet from soc.decoder.isa.all import ISA +from soc.decoder.isa.test_caller import run_tst + + +class DecoderTestCase(FHDLTestCase): + + def test_load_store(self): + lst = ["addi 1, 0, 0x0010", + "addi 2, 0, 0x1234", + "stw 2, 0(1)", + "lwz 3, 0(1)"] + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program) + print(sim.gpr(1)) + self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) + + def run_tst_program(self, prog, initial_regs=[0] * 32): + simulator = run_tst(prog, initial_regs) + simulator.gpr.dump() + return simulator + if __name__ == "__main__": - radix = RADIX(None,None) #first test to avoid syntax errors - radix._walk_tree() - print("DONE") + unittest.main() -- 2.30.2