From f90a4b1e24e36943a343bd36315b6029dd6cd044 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 08:57:37 -0700 Subject: [PATCH] Missed this --- passes/pmgen/xilinx_dsp_CREG.pmg | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 2408d483a..a57043009 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -105,9 +105,10 @@ endcode // ####################### // Subpattern for matching against input registers, based on knowledge of the -// 'Q' input. Typically, this task would be handled by other Yosys passes -// such as dff2dffe, but since DSP inference happens much before this, these -// patterns have to be manually identified. +// 'Q' input. Typically, identifying registers with clock-enable and reset +// capability would be a task would be handled by other Yosys passes such as +// dff2dffe, but since DSP inference happens much before this, these patterns +// have to be manually identified. // At a high level: // (1) Starting from a $dff cell that (partially or fully) drives the given // 'Q' argument -- 2.30.2