From f91ee5104b33f9b1b04a4bd16fb147407f448ded Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Jan 2020 11:36:31 +0000 Subject: [PATCH] --- 3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn index 0b1e18d1d..dd0f36582 100644 --- a/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn @@ -1,5 +1,13 @@ # Dynamic Partitioned SIMD +To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed. + +Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed. + +Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs. Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results. + +Pages below describe the basic features of each and track the relevant bugreports. + * [[3d_gpu/architecture/dynamic_simd/eq]] * [[3d_gpu/architecture/dynamic_simd/add]] * [[3d_gpu/architecture/dynamic_simd/mul]] -- 2.30.2