From f92113c5a1c1e928a2f50c78866f43eff4cd6630 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 1 Oct 2016 00:46:39 +0200 Subject: [PATCH] radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Caches are always flushed at IB boundary. Reviewed-by: Nicolai Hähnle Reviewed-by: Edward O'Callaghan --- src/gallium/drivers/radeonsi/si_state.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 443dc37078b..04b57dc5e03 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3414,14 +3414,13 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) if (flags & PIPE_BARRIER_FRAMEBUFFER) sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; - if (flags & (PIPE_BARRIER_MAPPED_BUFFER | - PIPE_BARRIER_FRAMEBUFFER | + if (flags & (PIPE_BARRIER_FRAMEBUFFER | PIPE_BARRIER_INDIRECT_BUFFER)) { /* Not sure if INV_GLOBAL_L2 is the best thing here. * * We need to make sure that TC L1 & L2 are written back to - * memory, because neither CPU accesses nor CB fetches consider - * TC, but there's no need to invalidate any TC cache lines. */ + * memory, because CB fetches don't consider TC, but there's + * no need to invalidate any TC cache lines. */ sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; } } -- 2.30.2