From f944d7c3f4aa9b43f9e204a662d3a7192ab41ee9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Apr 2019 11:09:54 +0100 Subject: [PATCH] more cases of Elaboratable --- src/add/fpadd/add0.py | 4 ++-- src/add/fpadd/add1.py | 4 ++-- src/add/fpbase.py | 12 ++++++------ src/add/fpcommon/corrections.py | 4 ++-- src/add/fpcommon/getop.py | 4 ++-- src/add/fpcommon/normtopack.py | 3 ++- src/add/fpcommon/pack.py | 4 ++-- src/add/fpcommon/postnormalise.py | 4 ++-- src/add/fpcommon/roundz.py | 4 ++-- 9 files changed, 22 insertions(+), 21 deletions(-) diff --git a/src/add/fpadd/add0.py b/src/add/fpadd/add0.py index 7d84b74c..76790fe2 100644 --- a/src/add/fpadd/add0.py +++ b/src/add/fpadd/add0.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Cat +from nmigen import Module, Signal, Cat, Elaboratable from nmigen.cli import main, verilog from fpbase import FPNumBase @@ -24,7 +24,7 @@ class FPAddStage0Data: self.tot.eq(i.tot), self.mid.eq(i.mid)] -class FPAddStage0Mod: +class FPAddStage0Mod(Elaboratable): def __init__(self, width, id_wid): self.width = width diff --git a/src/add/fpadd/add1.py b/src/add/fpadd/add1.py index 08c27b8e..679f5176 100644 --- a/src/add/fpadd/add1.py +++ b/src/add/fpadd/add1.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal +from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog from math import log @@ -11,7 +11,7 @@ from fpcommon.postcalc import FPAddStage1Data from fpadd.add0 import FPAddStage0Data -class FPAddStage1Mod(FPState): +class FPAddStage1Mod(FPState, Elaboratable): """ Second stage of add: preparation for normalisation. detects when tot sum is too big (tot[27] is kinda a carry bit) """ diff --git a/src/add/fpbase.py b/src/add/fpbase.py index 66cc8c0e..8f5094c1 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Signal, Cat, Const, Mux, Module +from nmigen import Signal, Cat, Const, Mux, Module, Elaboratable from math import log from operator import or_ from functools import reduce @@ -60,7 +60,7 @@ class MultiShift: return res -class FPNumBase: +class FPNumBase: #(Elaboratable): """ Floating-point Base Number Class """ def __init__(self, width, m_extra=True): @@ -214,7 +214,7 @@ class FPNumOut(FPNumBase): return self.create2(s, self.N127, self.mzero) -class MultiShiftRMerge: +class MultiShiftRMerge(Elaboratable): """ shifts down (right) and merges lower bits into m[0]. m[0] is the "sticky" bit, basically """ @@ -257,7 +257,7 @@ class MultiShiftRMerge: return m -class FPNumShift(FPNumBase): +class FPNumShift(FPNumBase, Elaboratable): """ Floating-point Number Class for shifting """ def __init__(self, mainm, op, inv, width, m_extra=True): @@ -464,7 +464,7 @@ class FPNumIn(FPNumBase): self.m.eq(sm.lshift(self.m, maxslen)) ] -class Trigger: +class Trigger(Elaboratable): def __init__(self): self.stb = Signal(reset=0) @@ -537,7 +537,7 @@ class FPOpOut(NextControl): ] -class Overflow: +class Overflow(Elaboratable): def __init__(self): self.guard = Signal(reset_less=True) # tot[2] self.round_bit = Signal(reset_less=True) # tot[1] diff --git a/src/add/fpcommon/corrections.py b/src/add/fpcommon/corrections.py index 166610c3..ce9ba3cd 100644 --- a/src/add/fpcommon/corrections.py +++ b/src/add/fpcommon/corrections.py @@ -2,13 +2,13 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module +from nmigen import Module, Elaboratable from nmigen.cli import main, verilog from fpbase import FPState from fpcommon.roundz import FPRoundData -class FPCorrectionsMod: +class FPCorrectionsMod(Elaboratable): def __init__(self, width, id_wid): self.width = width diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py index 5b500522..96a03c3e 100644 --- a/src/add/fpcommon/getop.py +++ b/src/add/fpcommon/getop.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Cat, Mux, Array, Const +from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable from nmigen.lib.coding import PriorityEncoder from nmigen.cli import main, verilog from math import log @@ -17,7 +17,7 @@ from multipipe import PriorityCombMuxInPipe from fpbase import FPState -class FPGetOpMod: +class FPGetOpMod(Elaboratable): def __init__(self, width): self.in_op = FPOpIn(width) self.out_op = Signal(width) diff --git a/src/add/fpcommon/normtopack.py b/src/add/fpcommon/normtopack.py index 14814669..87d08125 100644 --- a/src/add/fpcommon/normtopack.py +++ b/src/add/fpcommon/normtopack.py @@ -37,7 +37,8 @@ class FPNormToPack(FPState, SimpleHandshake): rmod = FPRoundMod(self.width, self.id_wid) cmod = FPCorrectionsMod(self.width, self.id_wid) pmod = FPPackMod(self.width, self.id_wid) - chain = StageChain([nmod, rmod, cmod, pmod]) + stages = [nmod, rmod, cmod, pmod] + chain = StageChain(stages) chain.setup(m, i) self.out_z = pmod.ospec() diff --git a/src/add/fpcommon/pack.py b/src/add/fpcommon/pack.py index 97d69111..1464883c 100644 --- a/src/add/fpcommon/pack.py +++ b/src/add/fpcommon/pack.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal +from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog from fpbase import FPNumOut @@ -19,7 +19,7 @@ class FPPackData(Object): self.mid = Signal(id_wid, reset_less=True) -class FPPackMod: +class FPPackMod(Elaboratable): def __init__(self, width, id_wid): self.width = width diff --git a/src/add/fpcommon/postnormalise.py b/src/add/fpcommon/postnormalise.py index c60adbca..b072490f 100644 --- a/src/add/fpcommon/postnormalise.py +++ b/src/add/fpcommon/postnormalise.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Cat, Mux +from nmigen import Module, Signal, Cat, Mux, Elaboratable from nmigen.lib.coding import PriorityEncoder from nmigen.cli import main, verilog from math import log @@ -27,7 +27,7 @@ class FPNorm1Data: self.roundz.eq(i.roundz), self.mid.eq(i.mid)] -class FPNorm1ModSingle: +class FPNorm1ModSingle(Elaboratable): def __init__(self, width, id_wid): self.width = width diff --git a/src/add/fpcommon/roundz.py b/src/add/fpcommon/roundz.py index 24c49b87..420d6669 100644 --- a/src/add/fpcommon/roundz.py +++ b/src/add/fpcommon/roundz.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal +from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog from fpbase import FPNumBase @@ -23,7 +23,7 @@ class FPRoundData: self.mid.eq(i.mid)] -class FPRoundMod: +class FPRoundMod(Elaboratable): def __init__(self, width, id_wid): self.width = width -- 2.30.2