From f95773a4132ed8f3249a6ae0eb4a37560ee7bb14 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Jul 2021 16:08:00 +0100
Subject: [PATCH] add SVREMAP SPR to ISACaller and parser

---
 src/openpower/decoder/isa/caller.py    | 10 ++++
 src/openpower/decoder/isa/svremap.py   | 80 ++++++++++++++++++++++++++
 src/openpower/decoder/pseudo/parser.py |  3 +-
 3 files changed, 92 insertions(+), 1 deletion(-)
 create mode 100644 src/openpower/decoder/isa/svremap.py

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e2cf01eb..3adc94bd 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -36,6 +36,8 @@ from openpower.decoder.power_svp64 import SVP64RM, decode_extra
 from openpower.decoder.isa.radixmmu import RADIX
 from openpower.decoder.isa.mem import Mem, swap_order, MemException
 from openpower.decoder.isa.svshape import SVSHAPE
+from openpower.decoder.isa.svremap import SVREMAP
+
 
 from openpower.util import log
 
@@ -613,6 +615,13 @@ class ISACaller:
                 val = self.spr[sname].value
                 self.spr[sname] = SVSHAPE(val)
         self.last_op_svshape = False
+        # and an SVREMAP
+        if 'SVREMAP' not in self.spr:
+            self.spr['SVREMAP'] = SVREMAP(0)
+        else:
+            # make sure it's an SVREMAP
+            val = self.spr['SVREMAP'].value
+            self.spr['SVREMAP'] = SVREMAP(val)
 
         # "raw" memory
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
@@ -653,6 +662,7 @@ class ISACaller:
                                'NIA': self.pc.NIA,
                                'CIA': self.pc.CIA,
                                'SVSTATE': self.svstate.spr,
+                               'SVREMAP': self.spr['SVREMAP'],
                                'SVSHAPE0': self.spr['SVSHAPE0'],
                                'SVSHAPE1': self.spr['SVSHAPE1'],
                                'SVSHAPE2': self.spr['SVSHAPE2'],
diff --git a/src/openpower/decoder/isa/svremap.py b/src/openpower/decoder/isa/svremap.py
new file mode 100644
index 00000000..f7697194
--- /dev/null
+++ b/src/openpower/decoder/isa/svremap.py
@@ -0,0 +1,80 @@
+from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+                                        selectconcat)
+from openpower.decoder.isa.remapyield import iterate_indices
+from openpower.decoder.isa.remap_fft_yield import iterate_butterfly_indices
+from openpower.sv.svp64 import SVP64REMAP
+import os
+from copy import deepcopy
+from openpower.util import log
+
+
+class SVREMAP(SelectableInt):
+    def __init__(self, value):
+        SelectableInt.__init__(self, value, 32)
+        offs = 0
+        # set up sub-fields from Record layout
+        self.fsi = {}
+        l = deepcopy(SVP64REMAP.layout)
+        l.reverse()
+        for field, width in l:
+            end =  offs+width
+            fs = tuple(range(offs, end))
+            v = FieldSelectableInt(self, fs)
+            self.fsi[field] = v
+            #log("SVREMAP setup field", field, offs, end)
+            offs = end
+
+    @property
+    def mi0(self):
+        mi0 = self.fsi['mi0'].asint(msb0=True)
+        return SVP64REMAP.mi0(mi0)
+
+    @mi0.setter
+    def mi0(self, value):
+        self.fsi['mi0'].eq(mi0)
+
+    @property
+    def mi1(self):
+        mi1 = self.fsi['mi1'].asint(msb0=True)
+        return SVP64REMAP.mi1(mi1)
+
+    @mi1.setter
+    def mi1(self, value):
+        self.fsi['mi1'].eq(mi1)
+
+    @property
+    def mi2(self):
+        mi2 = self.fsi['mi2'].asint(msb0=True)
+        return SVP64REMAP.mi2(mi2)
+
+    @mi2.setter
+    def mi2(self, value):
+        self.fsi['mi2'].eq(mi2)
+
+    @property
+    def mo0(self):
+        mo0 = self.fsi['mo0'].asint(msb0=True)
+        return SVP64REMAP.mo0(mo0)
+
+    @mo0.setter
+    def mo0(self, value):
+        self.fsi['mo0'].eq(mo0)
+
+    @property
+    def mo1(self):
+        mo1 = self.fsi['mo1'].asint(msb0=True)
+        return SVP64REMAP.mo1(mo1)
+
+    @mo1.setter
+    def mo1(self, value):
+        self.fsi['mo1'].eq(mo1)
+
+    @property
+    def men(self):
+        men = self.fsi['men'].asint(msb0=True)
+        return SVP64REMAP.men(men)
+
+    @men.setter
+    def men(self, value):
+        self.fsi['men'].eq(men)
+
diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index e32d25a3..2d6d295e 100644
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -728,7 +728,8 @@ class PowerParser:
             if name in ['CA', 'CA32']:
                 self.write_regs.add(name)
         if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR',
-                     'SVSTATE', 'SVSHAPE0', 'SVSHAPE1', 'SVSHAPE2', 'SVSHAPE3']:
+                     'SVSTATE', 'SVREMAP',
+                     'SVSHAPE0', 'SVSHAPE1', 'SVSHAPE2', 'SVSHAPE3']:
             self.special_regs.add(name)
             self.write_regs.add(name)  # and add to list to write
         p[0] = ast.Name(id=name, ctx=ast.Load())
-- 
2.30.2