From f95bd50b4c1879ca96f0d3f0a60fcebe4afc9aef Mon Sep 17 00:00:00 2001 From: Yeting Kuo Date: Thu, 17 Sep 2020 15:29:27 -0600 Subject: [PATCH] RISC-V: fix a typo in riscv.h gcc/ChangeLog: * config/riscv/riscv.h (CSW_MAX_OFFSET): Fix typo. gcc/testsuite/ChangeLog: * gcc.target/riscv/shorten-memrefs-8.c: New test. --- gcc/config/riscv/riscv.h | 2 +- .../gcc.target/riscv/shorten-memrefs-8.c | 27 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 9f67d82e74e..b7b4a1c88a5 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -941,7 +941,7 @@ extern unsigned riscv_stack_boundary; /* This is the maximum value that can be represented in a compressed load/store offset (an unsigned 5-bit value scaled by 4). */ -#define CSW_MAX_OFFSET ((4LL << C_S_BITS) - 1) & ~3 +#define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) /* Called from RISCV_REORG, this is defined in riscv-sr.c. */ diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c new file mode 100644 index 00000000000..a9128caeea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c @@ -0,0 +1,27 @@ +/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */ + +/* shorten_memrefs should use a correct base address*/ + +void +store (char *p, int k) +{ + *(int *)(p + 17) = k; + *(int *)(p + 21) = k; + *(int *)(p + 25) = k; + *(int *)(p + 29) = k; +} + +int +load (char *p) +{ + int a = 0; + a += *(int *)(p + 17); + a += *(int *)(p + 21); + a += *(int *)(p + 25); + a += *(int *)(p + 29); + return a; +} + +/* { dg-final { scan-assembler "store:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ +/* { dg-final { scan-assembler "load:\n\taddi\ta\[0-7\],a\[0-7\],1" } } */ + -- 2.30.2