From f96867893703000a4f2bc3c4a94772c2e6d5c276 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 16 Dec 2018 23:52:47 +0000 Subject: [PATCH] back.rtlil: handle reset_less domains. --- nmigen/back/rtlil.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 1836d75..67ffdd3 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -515,7 +515,8 @@ def convert_fragment(builder, fragment, name, top): for domain, _ in fragment.iter_sync(): cd = fragment.domains[domain] compiler_state.resolve_curr(cd.clk) - compiler_state.resolve_curr(cd.rst) + if cd.rst is not None: + compiler_state.resolve_curr(cd.rst) # Transform all subfragments to their respective cells. Transforming signals connected # to their ports into wires eagerly makes sure they get sensible (prefixed with submodule -- 2.30.2