From f969241e66e5c302d66a28d3f6ae5ce6fee19350 Mon Sep 17 00:00:00 2001 From: Omair Javaid Date: Sat, 4 Jan 2014 00:15:31 +0500 Subject: [PATCH] gdb: ARM: Fix for bugs in push and ldm instructions decoding This patch corrects the register numbers and removes multiple loops in recording procedure of instructions involving multiple registers. gdb/ChangeLog: 2014-01-15 Omair Javaid * arm-tdep.c (thumb_record_misc): Update to correct logical error while recording ldm, ldmia and pop instructions. --- gdb/ChangeLog | 5 +++++ gdb/arm-tdep.c | 61 +++++++++++++++----------------------------------- 2 files changed, 23 insertions(+), 43 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index a3789bc71a1..ccc83402239 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2014-01-15 Omair Javaid + + * arm-tdep.c (thumb_record_misc): Update to correct logical + error while recording ldm, ldmia and pop instructions. + 2014-01-15 Omair Javaid * arm-tdep.c (struct arm_mem_r) : Change type to uint32_t. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 0b17998105a..c945cbd0717 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11778,26 +11778,15 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) while (register_bits) { if (register_bits & 0x00000001) - register_list[register_count++] = 1; + record_buf[index++] = register_count; register_bits = register_bits >> 1; + register_count++; } /* Extra space for Base Register and CPSR; wihtout optimization. */ - record_buf[register_count] = reg_src1; - record_buf[register_count + 1] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = register_count + 2; - - for (register_count = 0; register_count < no_of_regs; register_count++) - { - if (register_list[register_count]) - { - /* Register_count gives total no of registers - and dually working as reg number. */ - record_buf[index] = register_count; - index++; - } - } - + record_buf[index++] = reg_src1; + record_buf[index++] = ARM_PS_REGNUM; + arm_insn_r->reg_rec_count = index; } else { @@ -12201,22 +12190,15 @@ thumb_record_misc (insn_decode_record *thumb_insn_r) /* POP. */ register_bits = bits (thumb_insn_r->arm_insn, 0, 7); while (register_bits) - { - if (register_bits & 0x00000001) - register_list[register_count++] = 1; - register_bits = register_bits >> 1; - } - record_buf[register_count] = ARM_PS_REGNUM; - record_buf[register_count + 1] = ARM_SP_REGNUM; - thumb_insn_r->reg_rec_count = register_count + 2; - for (register_count = 0; register_count < 8; register_count++) - { - if (register_list[register_count]) - { - record_buf[index] = register_count; - index++; - } - } + { + if (register_bits & 0x00000001) + record_buf[index++] = register_count; + register_bits = register_bits >> 1; + register_count++; + } + record_buf[index++] = ARM_PS_REGNUM; + record_buf[index++] = ARM_SP_REGNUM; + thumb_insn_r->reg_rec_count = index; } else if (10 == opcode2) { @@ -12313,19 +12295,12 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) while (register_bits) { if (register_bits & 0x00000001) - register_list[register_count++] = 1; + record_buf[index++] = register_count; register_bits = register_bits >> 1; + register_count++; } - record_buf[register_count] = reg_src1; - thumb_insn_r->reg_rec_count = register_count + 1; - for (register_count = 0; register_count < 8; register_count++) - { - if (register_list[register_count]) - { - record_buf[index] = register_count; - index++; - } - } + record_buf[index++] = reg_src1; + thumb_insn_r->reg_rec_count = index; } else if (0 == opcode2) { -- 2.30.2