From f97d7ff44c7e392afc14831c6a54145674c4a1f4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 21:21:30 +0200 Subject: [PATCH] global: pep8 (E261, E271) --- examples/sim/basic2.py | 2 +- mibuild/generic_platform.py | 2 +- mibuild/platforms/kc705.py | 2 +- mibuild/platforms/lx9_microboard.py | 18 +++++++++--------- mibuild/platforms/minispartan6.py | 4 ++-- mibuild/platforms/pipistrello.py | 10 +++++----- mibuild/platforms/rhino.py | 20 ++++++++++---------- mibuild/platforms/sim.py | 2 +- mibuild/platforms/usrp_b100.py | 4 ++-- mibuild/platforms/versa.py | 4 ++-- mibuild/platforms/zedboard.py | 10 +++++----- mibuild/platforms/ztex_115d.py | 14 +++++++------- migen/bank/eventmanager.py | 8 ++++---- migen/fhdl/simplify.py | 2 +- migen/fhdl/specials.py | 2 +- migen/fhdl/structure.py | 4 ++-- migen/genlib/coding.py | 22 +++++++++++----------- migen/genlib/fifo.py | 4 ++-- migen/genlib/record.py | 12 ++++++------ migen/genlib/sort.py | 4 ++-- 20 files changed, 75 insertions(+), 75 deletions(-) diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py index 958e828a..95a44ada 100644 --- a/examples/sim/basic2.py +++ b/examples/sim/basic2.py @@ -17,7 +17,7 @@ class Counter(Module): # Only assert CE every second cycle. # => each counter value is held for two cycles. if selfp.simulator.cycle_counter % 2: - selfp.ce = 0 # This is how you write to a signal. + selfp.ce = 0 # This is how you write to a signal. else: selfp.ce = 1 print("Cycle: " + str(selfp.simulator.cycle_counter) + " Count: " + \ diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 6e9dee29..91a3937b 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -241,7 +241,7 @@ class GenericPlatform: if language is None: language = tools.language_by_filename(filename) if language is None: - language = "verilog" # default to Verilog + language = "verilog" # default to Verilog filename = os.path.abspath(filename) self.sources.add((filename, language)) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 16e302b1..64f39d97 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -52,7 +52,7 @@ _io = [ Subsignal("rx", Pins("M19")), IOStandard("LVCMOS25")), - ("spiflash", 0, # clock needs to be accessed through STARTUPE2 + ("spiflash", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("U19")), Subsignal("dq", Pins("P24", "R25", "R20", "R21")), IOStandard("LVCMOS25") diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index 8ce9bea6..ea0cb415 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -16,9 +16,9 @@ _io = [ ("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), # TI CDCE913 programmable triple-output PLL - ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz - ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz - ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz + ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz + ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz + ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz # Maxim DS1088LU oscillator, not populated ("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")), @@ -58,7 +58,7 @@ _io = [ ("ddram_clock", 0, Subsignal("p", Pins("G3")), Subsignal("n", Pins("G1")), - IOStandard("MOBILE_DDR")), # actually DIFF_ + IOStandard("MOBILE_DDR")), # actually DIFF_ # Micron MT46H32M16LFBF-5 LPDDR ("ddram", 0, @@ -69,7 +69,7 @@ _io = [ "M3 M1 N2 N1 T2 T1 U2 U1")), Subsignal("cke", Pins("H7")), Subsignal("we_n", Pins("E3")), - Subsignal("cs_n", Pins("K6")), # NC! + Subsignal("cs_n", Pins("K6")), # NC! Subsignal("cas_n", Pins("K5")), Subsignal("ras_n", Pins("L5")), Subsignal("dm", Pins("K3", "K4")), @@ -89,14 +89,14 @@ _io = [ Subsignal("col", Pins("M18"), Misc("PULLUP")), Subsignal("crs", Pins("N17"), Misc("PULLDOWN")), Subsignal("mdc", Pins("M16"), Misc("PULLDOWN")), - Subsignal("mdio", Pins("L18"), Misc("PULLUP")), # 1k5 ext PULLUP + Subsignal("mdio", Pins("L18"), Misc("PULLUP")), # 1k5 ext PULLUP Subsignal("rst_n", Pins("T18"), Misc("TIG")), Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")), - Subsignal("dv", Pins("P17"), Misc("PULLDOWN")), # MII - Subsignal("rx_er", Pins("N18"), Misc("PULLUP")), # auto MDIX + Subsignal("dv", Pins("P17"), Misc("PULLDOWN")), # MII + Subsignal("rx_er", Pins("N18"), Misc("PULLUP")), # auto MDIX Subsignal("tx_data", Pins("K18 K17 J18 J16")), Subsignal("tx_en", Pins("L17")), - Subsignal("tx_er", Pins("L16")), # NC! + Subsignal("tx_er", Pins("L16")), # NC! IOStandard("LVCMOS33")), ] diff --git a/mibuild/platforms/minispartan6.py b/mibuild/platforms/minispartan6.py index 11ec3235..5ebdabde 100644 --- a/mibuild/platforms/minispartan6.py +++ b/mibuild/platforms/minispartan6.py @@ -38,8 +38,8 @@ _io = [ ), ("serial", 0, - Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 - Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 + Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 + Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 ), ("audio", 0, diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py index 5f5c591d..0b510604 100644 --- a/mibuild/platforms/pipistrello.py +++ b/mibuild/platforms/pipistrello.py @@ -3,11 +3,11 @@ from mibuild.xilinx import XilinxPlatform from mibuild.xilinx.programmer import XC3SProg _io = [ - ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi - ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi - ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd - ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd - ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb + ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi + ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi + ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd + ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd + ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index ab03b9a5..5f766ff9 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -25,17 +25,17 @@ _io = [ Subsignal("we_n", Pins("W26")), Subsignal("oe_n", Pins("AA25")), Subsignal("ale_n", Pins("AA26")), - Subsignal("wait", Pins("AD26")), # WAIT1/BUSY0 + Subsignal("wait", Pins("AD26")), # WAIT1/BUSY0 IOStandard("LVCMOS33")), # Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side. # Numbers here are given on the FPGA side. - ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0 - ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1 - ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6 - ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2 - ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3 - ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4 - ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5 + ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0 + ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1 + ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6 + ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2 + ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3 + ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4 + ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5 # FMC150 ("fmc150_ctrl", 0, @@ -63,14 +63,14 @@ _io = [ Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33")) ), - ("ti_dac", 0, # DAC3283 + ("ti_dac", 0, # DAC3283 Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")), Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")), Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")), Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")), Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25")) ), - ("ti_adc", 0, # ADS62P49 + ("ti_adc", 0, # ADS62P49 Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")), Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")), Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")), diff --git a/mibuild/platforms/sim.py b/mibuild/platforms/sim.py index d072c17a..55dec467 100644 --- a/mibuild/platforms/sim.py +++ b/mibuild/platforms/sim.py @@ -36,7 +36,7 @@ _io = [ class Platform(SimPlatform): is_sim = True default_clk_name = "sys_clk" - default_clk_period = 1000 # on modern computers simulate at ~ 1MHz + default_clk_period = 1000 # on modern computers simulate at ~ 1MHz def __init__(self): SimPlatform.__init__(self, "SIM", _io) diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py index 6edfe77b..9e956a03 100644 --- a/mibuild/platforms/usrp_b100.py +++ b/mibuild/platforms/usrp_b100.py @@ -33,8 +33,8 @@ _io = [ Subsignal("d", Pins("P8 P9 N9 T9 R9 P11 P13 N12 " "T3 R3 P5 N6 T6 T5 N8 P7")), Subsignal("ctl", Pins("M7 M9 M11 P12")), - Subsignal("slwr", Pins("T4")), # rdy0 - Subsignal("slrd", Pins("R5")), # rdy1 + Subsignal("slwr", Pins("T4")), # rdy0 + Subsignal("slrd", Pins("R5")), # rdy1 #Subsignal("rdy2", Pins("T10")), #Subsignal("rdy3", Pins("N11")), #Subsignal("cs", Pins("P12")), diff --git a/mibuild/platforms/versa.py b/mibuild/platforms/versa.py index 4a0d2794..e164bdec 100644 --- a/mibuild/platforms/versa.py +++ b/mibuild/platforms/versa.py @@ -28,8 +28,8 @@ _io = [ ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")), ("serial", 0, - Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0 - Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1 + Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0 + Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1 ), ("eth_clocks", 0, diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index a5a26743..72a799aa 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -5,11 +5,11 @@ from mibuild.xilinx import XilinxPlatform _io = [ ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), - ("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center - ("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down - ("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left - ("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right - ("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up + ("user_btn", 0, Pins("P16"), IOStandard("LVCMOS18")), # center + ("user_btn", 1, Pins("R16"), IOStandard("LVCMOS18")), # down + ("user_btn", 2, Pins("N15"), IOStandard("LVCMOS18")), # left + ("user_btn", 3, Pins("R18"), IOStandard("LVCMOS18")), # right + ("user_btn", 4, Pins("T18"), IOStandard("LVCMOS18")), # up ("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")), ("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")), diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index 7ca6afde..238d64dd 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -8,15 +8,15 @@ _io = [ # PROG_B and DONE: AA1 U16 ("fx2", 0, - Subsignal("sloe", Pins("U15"), Drive(12)), # M1 + Subsignal("sloe", Pins("U15"), Drive(12)), # M1 Subsignal("slrd", Pins("N22"), Drive(12)), Subsignal("slwr", Pins("M22"), Drive(12)), - Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO - Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 + Subsignal("pktend", Pins("AB5"), Drive(12)), # CSO + Subsignal("fifoadr", Pins("W17 Y18"), Drive(12)), # CCLK M0 Subsignal("cont", Pins("G20")), Subsignal("fd", Pins("Y17 V13 W13 AA8 AB8 W6 Y6 Y9 " "V21 V22 U20 U22 R20 R22 P18 P19")), - Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI + Subsignal("flag", Pins("F20 F19 F18 AB17")), # - - - CSI/MOSI Subsignal("rdy25", Pins("M21 K21 K22 J21")), Subsignal("ctl35", Pins("D19 E20 N20")), Subsignal("int45", Pins("C18 V17")), @@ -44,9 +44,9 @@ _io = [ IOStandard("SSTL18_II")), ("ddram", 0, - Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ + Subsignal("dqs", Pins("L3 T2"), IOStandard("SSTL18_II"), # DIFF_ Misc("IN_TERM=NONE")), - Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ + Subsignal("dqs_n", Pins("L1 T1"), IOStandard("SSTL18_II"), # DIFF_ Misc("IN_TERM=NONE")), Subsignal("dm", Pins("H1 H2"), Misc("OUT_TERM=UNTUNED_50")), Subsignal("dq", Pins("M1 M2 J1 K2 J3 K1 N3 N1 " @@ -57,7 +57,7 @@ _io = [ Misc("OUT_TERM=UNTUNED_50")), Subsignal("ba", Pins("E3 E1 D1"), Misc("OUT_TERM=UNTUNED_50")), Subsignal("cke", Pins("J6"), Misc("OUT_TERM=UNTUNED_50")), - Subsignal("cs_n", Pins("H6")), # NC! + Subsignal("cs_n", Pins("H6")), # NC! Subsignal("odt", Pins("M3"), Misc("OUT_TERM=UNTUNED_50")), Subsignal("we_n", Pins("D2")), Subsignal("rzq", Pins("AA2")), diff --git a/migen/bank/eventmanager.py b/migen/bank/eventmanager.py index effd4e61..1edfcb04 100644 --- a/migen/bank/eventmanager.py +++ b/migen/bank/eventmanager.py @@ -7,10 +7,10 @@ from migen.genlib.misc import optree class _EventSource(HUID): def __init__(self): HUID.__init__(self) - self.status = Signal() # value in the status register - self.pending = Signal() # value in the pending register + assert irq if unmasked - self.trigger = Signal() # trigger signal interface to the user design - self.clear = Signal() # clearing attempt by W1C to pending register, ignored by some event sources + self.status = Signal() # value in the status register + self.pending = Signal() # value in the pending register + assert irq if unmasked + self.trigger = Signal() # trigger signal interface to the user design + self.clear = Signal() # clearing attempt by W1C to pending register, ignored by some event sources # set on a positive trigger pulse diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py index 7c6a916b..66e4e58b 100644 --- a/migen/fhdl/simplify.py +++ b/migen/fhdl/simplify.py @@ -14,7 +14,7 @@ class FullMemoryWE(ModuleTransformer): continue global_granularity = gcd_multiple([p.we_granularity if p.we_granularity else orig.width for p in orig.ports]) if global_granularity == orig.width: - newspecials.add(orig) # nothing to do + newspecials.add(orig) # nothing to do else: for i in range(orig.width//global_granularity): if orig.init is None: diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index 5b504d01..7264e838 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -204,7 +204,7 @@ class _MemoryPort(Special): @staticmethod def emit_verilog(port, ns, add_data_file): - return "" # done by parent Memory object + return "" # done by parent Memory object class Memory(Special): diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index f2f424ae..45ab7945 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -264,7 +264,7 @@ class Signal(Value): min = 0 if max is None: max = 2 - max -= 1 # make both bounds inclusive + max -= 1 # make both bounds inclusive assert(min < max) self.signed = min < 0 or max < 0 self.nbits = builtins.max(bits_for(min, self.signed), bits_for(max, self.signed)) @@ -277,7 +277,7 @@ class Signal(Value): if not isinstance(self.nbits, int) or self.nbits <= 0: raise ValueError("Signal width must be a strictly positive integer") - self.variable = variable # deprecated + self.variable = variable # deprecated self.reset = reset self.name_override = name_override self.backtrace = tracer.trace_back(name) diff --git a/migen/genlib/coding.py b/migen/genlib/coding.py index 21366f2c..5d1231e9 100644 --- a/migen/genlib/coding.py +++ b/migen/genlib/coding.py @@ -26,9 +26,9 @@ class Encoder(Module): Invalid, either none or multiple input bits are asserted """ def __init__(self, width): - self.i = Signal(width) # one-hot - self.o = Signal(max=max(2, width)) # binary - self.n = Signal() # invalid: none or multiple + self.i = Signal(width) # one-hot + self.o = Signal(max=max(2, width)) # binary + self.n = Signal() # invalid: none or multiple act = dict((1< 1: t = [Signal(m) for j in range(n)] - self._sort(i[:k], t[:k], 1, m) # ascending - self._sort(i[k:], t[k:], 0, m) # descending + self._sort(i[:k], t[:k], 1, m) # ascending + self._sort(i[k:], t[k:], 0, m) # descending self._merge(t, o, dir, m) else: self.comb += o[0].eq(i[0]) -- 2.30.2