From f9849fb8be4d5c5c14be3164192f6f2d614049c4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 10 Sep 2015 20:32:47 -0700 Subject: [PATCH] style --- migen/fhdl/verilog.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 39d87d75..84031334 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -8,6 +8,7 @@ from migen.fhdl.bitcontainer import bits_for, flen from migen.fhdl.namer import Namespace, build_namespace from migen.fhdl.conv_output import ConvOutput + _reserved_keywords = { "always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1", "case", "casex", "casez", "cell", "cmos", "config", "deassign", "default", @@ -25,7 +26,8 @@ _reserved_keywords = { "specparam", "strong0", "strong1", "supply0", "supply1", "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait", "wand", "weak0", -"weak1", "while", "wire", "wor","xnor","xor"} +"weak1", "while", "wire", "wor","xnor","xor" +} def _printsig(ns, s): @@ -116,6 +118,7 @@ def _printexpr(ns, node): else: raise TypeError("Expression of unrecognized type: "+str(type(node))) + (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3) -- 2.30.2