From f986974d608bae6f5e6fe09c260d8c93729c817c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 15 Apr 2019 10:57:00 +0200 Subject: [PATCH] soc/cores/clock: improve presentation --- litex/soc/cores/clock.py | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 785d971c..e50dd1a0 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -1,9 +1,4 @@ -""" -Clock Abstraction Modules - - -Made in Paris-CDG while waiting a delayed Air-France KLM flight... -""" +"""Clock Abstraction Modules""" from migen import * from migen.genlib.io import DifferentialInput @@ -15,7 +10,7 @@ from litex.soc.interconnect.csr import * def period_ns(freq): return 1e9/freq -# Xilinx / 7-Series +# Xilinx / 7-Series -------------------------------------------------------------------------------- class S7Clocking(Module, AutoCSR): clkfbout_mult_frange = (2, 64+1) @@ -204,7 +199,7 @@ class S7IDELAYCTRL(Module): ) self.specials += Instance("IDELAYCTRL", i_REFCLK=cd.clk, i_RST=ic_reset) -# Xilinx / Ultrascale +# Xilinx / Ultrascale ------------------------------------------------------------------------------ # TODO: # - use Ultrascale primitives instead of 7-Series' ones. (Vivado recognize and convert them). @@ -404,7 +399,7 @@ class USIDELAYCTRL(Module): i_REFCLK=cd.clk, i_RST=ic_reset) -# Lattice / ECP5 +# Lattice / ECP5 ----------------------------------------------------------------------------------- # TODO: # - add proper phase support. -- 2.30.2