From f9acee4e68471c0084cb1247f688d0d02edfb982 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 22 Feb 2013 23:19:37 +0100 Subject: [PATCH] corelogic -> genlib --- examples/basic/complex.py | 2 +- examples/basic/fsm.py | 2 +- examples/basic/namer.py | 2 +- examples/basic/two_dividers.py | 2 +- examples/basic/using_record.py | 2 +- examples/sim/fir.py | 2 +- migen/actorlib/dma_asmi.py | 2 +- migen/actorlib/misc.py | 4 ++-- migen/bank/eventmanager.py | 2 +- migen/bus/asmibus.py | 2 +- migen/bus/simple.py | 2 +- migen/bus/wishbone.py | 4 ++-- migen/bus/wishbone2asmi.py | 6 +++--- migen/bus/wishbone2csr.py | 2 +- migen/flow/actor.py | 4 ++-- migen/flow/network.py | 2 +- migen/flow/plumbing.py | 4 ++-- migen/{corelogic => genlib}/__init__.py | 0 migen/{corelogic => genlib}/buffers.py | 0 migen/{corelogic => genlib}/complex.py | 0 migen/{corelogic => genlib}/divider.py | 0 migen/{corelogic => genlib}/fsm.py | 0 migen/{corelogic => genlib}/misc.py | 0 migen/{corelogic => genlib}/record.py | 0 migen/{corelogic => genlib}/roundrobin.py | 0 migen/pytholite/fsm.py | 2 +- 26 files changed, 24 insertions(+), 24 deletions(-) rename migen/{corelogic => genlib}/__init__.py (100%) rename migen/{corelogic => genlib}/buffers.py (100%) rename migen/{corelogic => genlib}/complex.py (100%) rename migen/{corelogic => genlib}/divider.py (100%) rename migen/{corelogic => genlib}/fsm.py (100%) rename migen/{corelogic => genlib}/misc.py (100%) rename migen/{corelogic => genlib}/record.py (100%) rename migen/{corelogic => genlib}/roundrobin.py (100%) diff --git a/examples/basic/complex.py b/examples/basic/complex.py index d0e61e5e..8404cec5 100644 --- a/examples/basic/complex.py +++ b/examples/basic/complex.py @@ -1,4 +1,4 @@ -from migen.corelogic.complex import * +from migen.genlib.complex import * from migen.fhdl import verilog w = Complex(32, 42) diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py index f1716aea..4eedd97e 100644 --- a/examples/basic/fsm.py +++ b/examples/basic/fsm.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * from migen.fhdl import verilog -from migen.corelogic.fsm import FSM +from migen.genlib.fsm import FSM s = Signal() myfsm = FSM("FOO", "BAR") diff --git a/examples/basic/namer.py b/examples/basic/namer.py index 2928c840..80f86b54 100644 --- a/examples/basic/namer.py +++ b/examples/basic/namer.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * from migen.fhdl import verilog -from migen.corelogic.misc import optree +from migen.genlib.misc import optree def gen_list(n): s = [Signal() for i in range(n)] diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py index d82f8af1..1d15aea2 100644 --- a/examples/basic/two_dividers.py +++ b/examples/basic/two_dividers.py @@ -1,5 +1,5 @@ from migen.fhdl import verilog -from migen.corelogic import divider +from migen.genlib import divider d1 = divider.Divider(16) d2 = divider.Divider(16) diff --git a/examples/basic/using_record.py b/examples/basic/using_record.py index 8e715a51..15988e83 100644 --- a/examples/basic/using_record.py +++ b/examples/basic/using_record.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * -from migen.corelogic.record import * +from migen.genlib.record import * L = [ ("x", 10, 8), diff --git a/examples/sim/fir.py b/examples/sim/fir.py index a2369503..e113154a 100644 --- a/examples/sim/fir.py +++ b/examples/sim/fir.py @@ -7,7 +7,7 @@ import matplotlib.pyplot as plt from migen.fhdl.structure import * from migen.fhdl import verilog -from migen.corelogic.misc import optree +from migen.genlib.misc import optree from migen.fhdl import autofragment from migen.sim.generic import Simulator, PureSimulable diff --git a/migen/actorlib/dma_asmi.py b/migen/actorlib/dma_asmi.py index 1f6d5d0b..65d05ca8 100644 --- a/migen/actorlib/dma_asmi.py +++ b/migen/actorlib/dma_asmi.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * from migen.flow.actor import * -from migen.corelogic.buffers import ReorderBuffer +from migen.genlib.buffers import ReorderBuffer class SequentialReader(Actor): def __init__(self, port): diff --git a/migen/actorlib/misc.py b/migen/actorlib/misc.py index 0115f56f..b0799706 100644 --- a/migen/actorlib/misc.py +++ b/migen/actorlib/misc.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * -from migen.corelogic.record import * -from migen.corelogic.fsm import * +from migen.genlib.record import * +from migen.genlib.fsm import * from migen.flow.actor import * # Generates integers from start to maximum-1 diff --git a/migen/bank/eventmanager.py b/migen/bank/eventmanager.py index 298ec44a..200803ed 100644 --- a/migen/bank/eventmanager.py +++ b/migen/bank/eventmanager.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * from migen.bank.description import * -from migen.corelogic.misc import optree +from migen.genlib.misc import optree class EventSource: def __init__(self): diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py index ff7b1927..cab327a7 100644 --- a/migen/bus/asmibus.py +++ b/migen/bus/asmibus.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * -from migen.corelogic.misc import optree +from migen.genlib.misc import optree from migen.bus.transactions import * from migen.sim.generic import Proxy, PureSimulable diff --git a/migen/bus/simple.py b/migen/bus/simple.py index 062b9e75..8c6e0d68 100644 --- a/migen/bus/simple.py +++ b/migen/bus/simple.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * -from migen.corelogic.misc import optree +from migen.genlib.misc import optree (S_TO_M, M_TO_S) = range(2) diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py index fb7ec125..23abfa6e 100644 --- a/migen/bus/wishbone.py +++ b/migen/bus/wishbone.py @@ -1,7 +1,7 @@ from migen.fhdl.structure import * from migen.fhdl.specials import Memory -from migen.corelogic import roundrobin -from migen.corelogic.misc import optree +from migen.genlib import roundrobin +from migen.genlib.misc import optree from migen.bus.simple import * from migen.bus.transactions import * from migen.sim.generic import Proxy, PureSimulable diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py index 0fccefcc..c68999cb 100644 --- a/migen/bus/wishbone2asmi.py +++ b/migen/bus/wishbone2asmi.py @@ -1,9 +1,9 @@ from migen.fhdl.structure import * from migen.fhdl.specials import Memory from migen.bus import wishbone -from migen.corelogic.fsm import FSM -from migen.corelogic.misc import split, displacer, chooser -from migen.corelogic.record import Record +from migen.genlib.fsm import FSM +from migen.genlib.misc import split, displacer, chooser +from migen.genlib.record import Record # cachesize (in 32-bit words) is the size of the data store, must be a power of 2 class WB2ASMI: diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py index b8018662..5e62de84 100644 --- a/migen/bus/wishbone2csr.py +++ b/migen/bus/wishbone2csr.py @@ -1,7 +1,7 @@ from migen.bus import wishbone from migen.bus import csr from migen.fhdl.structure import * -from migen.corelogic.misc import timeline +from migen.genlib.misc import timeline class WB2CSR: def __init__(self): diff --git a/migen/flow/actor.py b/migen/flow/actor.py index 15eee8c2..ce46638d 100644 --- a/migen/flow/actor.py +++ b/migen/flow/actor.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * -from migen.corelogic.misc import optree -from migen.corelogic.record import * +from migen.genlib.misc import optree +from migen.genlib.record import * class Endpoint: def __init__(self, token): diff --git a/migen/flow/network.py b/migen/flow/network.py index 494d906e..df739eef 100644 --- a/migen/flow/network.py +++ b/migen/flow/network.py @@ -1,7 +1,7 @@ from networkx import MultiDiGraph from migen.fhdl.structure import * -from migen.corelogic.misc import optree +from migen.genlib.misc import optree from migen.flow.actor import * from migen.flow import plumbing from migen.flow.isd import DFGReporter diff --git a/migen/flow/plumbing.py b/migen/flow/plumbing.py index 7c30f760..04fc5d12 100644 --- a/migen/flow/plumbing.py +++ b/migen/flow/plumbing.py @@ -1,7 +1,7 @@ from migen.fhdl.structure import * from migen.flow.actor import * -from migen.corelogic.record import * -from migen.corelogic.misc import optree +from migen.genlib.record import * +from migen.genlib.misc import optree class Buffer(PipelinedActor): def __init__(self, layout): diff --git a/migen/corelogic/__init__.py b/migen/genlib/__init__.py similarity index 100% rename from migen/corelogic/__init__.py rename to migen/genlib/__init__.py diff --git a/migen/corelogic/buffers.py b/migen/genlib/buffers.py similarity index 100% rename from migen/corelogic/buffers.py rename to migen/genlib/buffers.py diff --git a/migen/corelogic/complex.py b/migen/genlib/complex.py similarity index 100% rename from migen/corelogic/complex.py rename to migen/genlib/complex.py diff --git a/migen/corelogic/divider.py b/migen/genlib/divider.py similarity index 100% rename from migen/corelogic/divider.py rename to migen/genlib/divider.py diff --git a/migen/corelogic/fsm.py b/migen/genlib/fsm.py similarity index 100% rename from migen/corelogic/fsm.py rename to migen/genlib/fsm.py diff --git a/migen/corelogic/misc.py b/migen/genlib/misc.py similarity index 100% rename from migen/corelogic/misc.py rename to migen/genlib/misc.py diff --git a/migen/corelogic/record.py b/migen/genlib/record.py similarity index 100% rename from migen/corelogic/record.py rename to migen/genlib/record.py diff --git a/migen/corelogic/roundrobin.py b/migen/genlib/roundrobin.py similarity index 100% rename from migen/corelogic/roundrobin.py rename to migen/genlib/roundrobin.py diff --git a/migen/pytholite/fsm.py b/migen/pytholite/fsm.py index 305a0cd4..7bc6c4c2 100644 --- a/migen/pytholite/fsm.py +++ b/migen/pytholite/fsm.py @@ -1,5 +1,5 @@ from migen.fhdl import visit as fhdl -from migen.corelogic.fsm import FSM +from migen.genlib.fsm import FSM class AbstractNextState: def __init__(self, target_state): -- 2.30.2