From f9c887ac068686a6b368ad3c1432ad8ba1d0b201 Mon Sep 17 00:00:00 2001 From: Zack Weinberg Date: Thu, 19 Feb 2004 21:39:52 +0000 Subject: [PATCH] ia64.c (ia64_function_arg): In big-endian mode... * config/ia64/ia64.c (ia64_function_arg): In big-endian mode, when passing single SFmode quantities in general registers, put them in the high half. From-SVN: r78119 --- gcc/ChangeLog | 32 +++++++++++++++++++------------- gcc/config/ia64/ia64.c | 21 +++++++++++++++++---- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0c8a7d2728c..69b4b597f1e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,19 +1,25 @@ +2004-02-19 Zack Weinberg + + * config/ia64/ia64.c (ia64_function_arg): In big-endian mode, + when passing single SFmode quantities in general registers, + put them in the high half. + 2004-02-19 Aldy Hernandez - - * doc/md.texi (Standard Names): Document additional dependency on - fix pattern. - - * optabs.c (ftruncify): Remove. - (expand_fix): Manually inline ftruncify above. - (can_fix_p): Add FIXME note. + + * doc/md.texi (Standard Names): Document additional dependency on + fix pattern. + + * optabs.c (ftruncify): Remove. + (expand_fix): Manually inline ftruncify above. + (can_fix_p): Add FIXME note. 2004-02-19 Aldy Hernandez - - * config/rs6000/spe.md (spe_fixunssfsi2): Rename to - spe_fixuns_truncsfsi2. - - * config/rs6000/rs6000.md (fixunssfsi2): Rename to - fixuns_truncsfsi2. + + * config/rs6000/spe.md (spe_fixunssfsi2): Rename to + spe_fixuns_truncsfsi2. + + * config/rs6000/rs6000.md (fixunssfsi2): Rename to + fixuns_truncsfsi2. 2004-02-19 Steve Ellcey diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f7e5cc341c7..b790819ca35 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -3786,21 +3786,34 @@ ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, named, and in a GR register when unnamed. */ else if (cum->prototype) { - if (! named) - return gen_rtx_REG (mode, basereg + cum->words + offset); - else + if (named) return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs); + /* In big-endian mode, an anonymous SFmode value must be represented + as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force + the value into the high half of the general register. */ + else if (BYTES_BIG_ENDIAN && mode == SFmode) + return gen_rtx_PARALLEL (mode, + gen_rtvec (1, + gen_rtx_EXPR_LIST (VOIDmode, + gen_rtx_REG (DImode, basereg + cum->words + offset), + const0_rtx))); + else + return gen_rtx_REG (mode, basereg + cum->words + offset); } /* If there is no prototype, then FP values go in both FR and GR registers. */ else { + /* See comment above. */ + enum machine_mode inner_mode = + (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode; + rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, (FR_ARG_FIRST + cum->fp_regs)), const0_rtx); rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, - gen_rtx_REG (mode, + gen_rtx_REG (inner_mode, (basereg + cum->words + offset)), const0_rtx); -- 2.30.2