From f9eddc8acf996a6d3dccc84216dac07ad4026032 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 15:55:50 +0100 Subject: [PATCH] use same write_vcd for cxxsim as pysim --- src/soc/fu/alu/test/test_pipe_caller.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index b2233ca8..a8a62f1c 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -248,12 +248,8 @@ class TestRunner(FHDLTestCase): yield from self.check_alu_outputs(alu, pdecode2, sim, code) sim.add_sync_process(process) - if cxxsim: - sim.run() - else: - with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw", - traces=[]): - sim.run() + sim.write_vcd("alu_simulator.vcd") + sim.run() def check_alu_outputs(self, alu, dec2, sim, code): -- 2.30.2