From f9f10c977d6fed060d6e34eeea8715e27a335f08 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 26 Apr 2023 17:11:46 +0100
Subject: [PATCH]

---
 openpower/sv/vector_ops/discussion.mdwn | 50 +------------------------
 1 file changed, 1 insertion(+), 49 deletions(-)

diff --git a/openpower/sv/vector_ops/discussion.mdwn b/openpower/sv/vector_ops/discussion.mdwn
index 9cefacda9..c9c57e0b3 100644
--- a/openpower/sv/vector_ops/discussion.mdwn
+++ b/openpower/sv/vector_ops/discussion.mdwn
@@ -143,57 +143,9 @@ with the appropriate predication
 
 # conflictd
 
-This is based on the AVX512 conflict detection instruction.  Internally the logic is used to detect address conflicts in multi-issue LD/ST operations.  Two arrays of values are given: the indices are compared and duplicates reported in a triangular fashion.  the instruction may be used for histograms (computed in parallel)
-
-    input = [100, 100,   3, 100,   5, 100, 100,   3]
-    conflict result = [
-         0b00000000,    // Note: first element always zero
-         0b00000001,    // 100 is present on #0
-         0b00000000,
-         0b00000011,    // 100 is present on #0 and #1
-         0b00000000,
-         0b00001011,    // 100 is present on #0, #1, #3
-         0b00011011,    // .. and #4
-         0b00000100     // 3 is present on #2
-    ]
-
-Pseudocode:
-
-    for i in range(VL):
-        for j in range(1, i):
-            if src1[i] == src2[j]:
-                result[j] |= 1<<i
-
-Idea 1: implement this as a Triangular Schedule, Vertical-First Mode,
-  using `mfcrweird` and `cmpi`. first triangular schedule on src1,
-secpnd on src2.
-
-Idea 2: implement using outer loop on varying setvl Horizontal-First
-with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into the
-result.
+moved to [[sv/cookbook/conflictd]]
 
-```
-    li r3, target
-    li result, 0
-    for i in range(target):
-        setvl target
-        addi r3, r3, -1 # shift 1<<r3 predicate down by one
-        sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
-        sv.cmpi src2.v, t0 # compare src2 vector to scalar
-        sv.mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
-        or result, result, t1
-```
-
-See [[sv/cr_int_predication]] for full details on the crweird instructions:
-the primary important aspect here is that a Vector of CR Field's EQ bits is
-transferred into a single GPR.  The secondary important aspect is that VL
-is being adjusted in each loop, testing successively more of the input
-vector against a given scalar, each time.
-
-To investigate:
 
-* <https://stackoverflow.com/questions/39266476/how-to-speed-up-this-histogram-of-lut-lookups>
-* <https://stackoverflow.com/questions/39913707/how-do-the-conflict-detection-instructions-make-it-easier-to-vectorize-loops>
 
 # iota
 
-- 
2.30.2