From f9fa4363858bbe008735b45d15b0c031ce5ca08b Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Thu, 9 Feb 2006 15:18:10 +0000 Subject: [PATCH] arm.md (tlobits_cbranch): New pattern. * arm.md (tlobits_cbranch): New pattern. * arm.h (arm_select_cc_mode): For thumb, only return CC_Nmode if testing a single bit. From-SVN: r110803 --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/arm.c | 3 ++- gcc/config/arm/arm.md | 44 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c339897488a..f3835d88c4d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-02-09 Richard Earnshaw + + * arm.md (tlobits_cbranch): New pattern. + * arm.h (arm_select_cc_mode): For thumb, only return CC_Nmode if + testing a single bit. + 2006-02-09 Andrew Pinski PR tree-opt/26179 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c7cb82c8e2d..4e9ae1b6e3f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6748,7 +6748,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) if (TARGET_THUMB && GET_MODE (x) == SImode && (op == EQ || op == NE) - && (GET_CODE (x) == ZERO_EXTRACT)) + && GET_CODE (x) == ZERO_EXTRACT + && XEXP (x, 1) == const1_rtx) return CC_Nmode; /* An operation that sets the condition codes as a side-effect, the diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3853afc1aac..53b633ddc7f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6028,6 +6028,50 @@ (const_int 8))))] ) +(define_insn "*tlobits_cbranch" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(zero_extract:SI (match_operand:SI 1 "s_register_operand" "l") + (match_operand:SI 2 "const_int_operand" "i") + (const_int 0)) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 4 "=l"))] + "TARGET_THUMB" + "* + { + rtx op[3]; + op[0] = operands[4]; + op[1] = operands[1]; + op[2] = GEN_INT (32 - INTVAL (operands[2])); + + output_asm_insn (\"lsl\\t%0, %1, %2\", op); + switch (get_attr_length (insn)) + { + case 4: return \"b%d0\\t%l3\"; + case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + (define_insn "*tstsi3_cbranch" [(set (pc) (if_then_else -- 2.30.2