From fa042c3e65379b665b0058cf62fd77f2c7a6bd3e Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 25 Dec 2020 17:34:44 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index e752c3145..291fad549 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -100,6 +100,7 @@ added in future revisions of SV. The rest of this document builds on the above simple loop to add: * Vector-Scalar, Scalar-Vector and Scalar-Scalar operation + (of all register files: Integer, FP *and CRs*) * Traditional Vector operations (VSPLAT, VINSERT, VCOMPRESS etc) * Predication masks (essential for parallel if/else constructs) * 8, 16 and 32 bit integer operations, and both FP16 and BF16. @@ -466,7 +467,7 @@ that there would be savings to be had in some types of operations where the post-result analysis, if not included in SV, would need a second predicate calculation followed by a predicate mask AND operation. -Note, hilariously, that Condition Register Operations (crand, cror) may +Note, hilariously, that Vectorised Condition Register Operations (crand, cror) may also have post-result analysis applied to them. With Vectors of CRs being utilised *for* predication, possibilities for compact and elegant code begin to emerge from this innocuous-looking addition to SV. -- 2.30.2