From fa04936c923065a24dba2393447ac6053548f9b3 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Sep 2019 15:54:09 +1000 Subject: [PATCH] Add some assertions to writeback We want to make sure we never complete more than one instruction per cycle, or write back more than one GPR or CR per cycle. Signed-off-by: Anton Blanchard --- writeback.vhdl | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/writeback.vhdl b/writeback.vhdl index e3e76e8..5a6bbe4 100644 --- a/writeback.vhdl +++ b/writeback.vhdl @@ -1,5 +1,6 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library work; use work.common.all; @@ -41,9 +42,21 @@ begin complete_out <= '1' when e.valid or l.valid or m.valid else '0'; writeback_1: process(all) + variable x: std_ulogic_vector(0 downto 0); + variable y: std_ulogic_vector(0 downto 0); + variable z: std_ulogic_vector(0 downto 0); begin - --assert (unsigned(w.valid) + unsigned(l.valid) + unsigned(m.valid)) <= 1; - --assert not(w.write_enable = '1' and l.write_enable = '1'); + x := "" & e.valid; + y := "" & l.valid; + z := "" & m.valid; + assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1; + + x := "" & e.write_enable; + y := "" & l.write_enable; + z := "" & m.write_reg_enable; + assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1; + + assert not(e.write_cr_enable = '1' and m.write_cr_enable = '1'); w_tmp <= WritebackToRegisterFileInit; c_tmp <= WritebackToCrFileInit; -- 2.30.2